參數(shù)資料
型號: MC68HCP11A1CP2
廠商: MOTOROLA INC
元件分類: 微控制器/微處理器
英文描述: HCMOS Single-Chip Microcontroller
中文描述: 8-BIT, 2 MHz, MICROCONTROLLER, PDIP48
封裝: DIP-48
文件頁數(shù): 108/158頁
文件大?。?/td> 776K
代理商: MC68HCP11A1CP2
MOTOROLA
10-10
CPU, ADDRESSING MODES, AND INSTRUCTION SET
MC68HC11A8
TECHNICAL DATA
10
ROR (opr)
Rotate Right
EXT
IND,X
IND,Y
A INH
B INH
76
66
18 66
46
56
hh ll
ff
ff
3
2
3
1
1
6
6
7
2
2
5-8
6-3
7-3
2-1
2-1
- - - -
¤ ¤ ¤ ¤
RORA
RORB
RTI
RTS
SBA
SBCA (opr) Subtract with Carry from A
Return from Interrupt
Return from Subroutine
Subtract B from A
See Special Ops
See Special Ops
A – B
A
A – M – C
A
INH
INH
INH
A IMM
A DIR
A EXT
A IND,X
A IND,Y
B IMM
B DIR
B EXT
B IND,X
B IND,Y
INH
INH
INH
A DIR
A EXT
A IND,X
A IND,Y
B DIR
B EXT
B IND,X
B IND,Y
DIR
EXT
IND,X
IND,Y
INH
DIR
EXT
IND,X
IND,Y
DIR
EXT
IND,X
IND,Y
DIR
EXT
IND,X
IND,Y
A IMM
A DIR
A EXT
A IND,X
A IND,Y
B IMM
B DIR
B EXT
B IND,X
B IND,Y
IMM
DlR
EXT
IND,X
IND,Y
INH
INH
INH
INH
3B
39
10
82
92
B2
A2
1
1
1
2
2
3
2
3
2
2
3
2
3
1
1
1
2
3
2
3
2
3
2
3
2
3
2
3
1
2
3
2
3
2
3
2
3
3
4
3
3
2
2
3
2
3
2
2
3
2
3
3
2
3
2
3
1
1
1
1
12
5
2
2
3
4
4
5
2
3
4
4
5
2
2
2
3
4
4
5
3
4
4
5
4
5
5
6
2
4
5
5
6
4
5
5
6
5
6
6
6
2
3
4
4
5
2
3
4
4
5
4
5
6
6
7
14
2
2
2
2-14
2-12
2-1
3-1
4-1
5-2
6-2
7-2
3-1
4-1
5-2
6-2
7-2
2-1
2-1
2-1
4-2
5-3
6-5
7-5
4-2
5-3
6-5
7-5
4-4
5-5
6-8
7-7
2-1
4-4
5-5
6-8
7-7
4-4
5-5
6-8
7-7
4-6
5-7
6-9
7-7
3-1
4-1
5-2
6-2
7-2
3-1
4-1
5-2
6-2
7-2
3-3
4-7
5-10
6-10
7-8
2-15
2-1
2-1
2-1
¤
¤ ¤ ¤ ¤ ¤ ¤
- - - - - - - -
- - - -
¤ ¤ ¤ ¤
- - - -
¤ ¤ ¤ ¤
18 A2
ii
dd
hh ll
ff
ff
ii
dd
hh ll
ff
ff
SBCB (opr) Subtract with Carry from B
B – M – C
B
C2
D2
F2
E2
18 E2
OD
OF
OB
- - - -
¤ ¤ ¤ ¤
SEC
SEI
SEV
STAA (opr) Store Accumulator A
Set Carry
Set Interrupt Mask
Set Overflow Flag
1
C
1
I
1
V
A
M
- - - - - - - 1
- - - 1 - - - -
- - - - - - 1 -
- - - -
¤ ¤
0 -
97
B7
A7
18 A7
dd
hh ll
ff
ff
dd
hh ll
ff
ff
dd
hh ll
ff
ff
STAB (opr) Store Accumulator B
B
M
D7
F7
E7
18 E7
DD
FD
ED
18 ED
- - - -
¤ ¤
0 -
STD (opr)
Store Accumulator D
A
M, B
M + 1
- - - -
¤ ¤
0 -
STOP
STS (opr)
Stop Internal Clocks
Store Stack Pointer
CF
9F
BF
AF
- - - - - - - -
- - - -
¤ ¤
0 -
SP
M:M + 1
18 AF
dd
hh ll
ff
ff
dd
hh ll
ff
ff
dd
hh ll
ff
ff
ii
dd
hh lI
ff
ff
ii
dd
hh ll
ff
ff
jj kk
dd
hh ll
ff
ff
STX (opr)
Store Index Register X
IX
M:M + 1
DF
FF
EF
CD EF
18 DF
18 FF
1A EF
18 EF
- - - -
¤ ¤
0 -
STY (opr)
Store Index Register Y
IY
M:M + 1
- - - -
¤ ¤
0 -
SUBA (opr) Subtract Memory from A
A – M
A
80
90
B0
A0
18 A0
- - - -
¤ ¤ ¤ ¤
SUBB (opr) Subtract Memory from B
B – M
B
C0
D0
F0
E0
18 E0
- - - -
¤ ¤ ¤ ¤
SUBD (opr) Subtract Memory from D
D – M:M + 1
D
83
93
B3
A3
18 A3
- - - -
¤ ¤ ¤ ¤
SWI
TAB
TAP
TBA
*Cycle-by-cycle number provides a reference to Tables 10-2 through 10-8 which detail cycle-by-cycle operation.
Example: Table 10-1 Cycle-by-Cycle column reference number 2-4 equals Table 10-2 line item 2-4.
Software Interrupt
Transfer A to B
Transfer A to CC Register
Transfer B to A
See Special Ops
A
B
A
CCR
B
A
3F
16
06
17
- - - 1- - - -
- - - -
¤ ¤
0 -
¤
¤ ¤ ¤ ¤ ¤ ¤
- - - -
¤ ¤
0 -
Table 10-1 MC68HC11A8 Instructions, Addressing Modes, and Execution Times
(Sheet 5 of 6)
Source
Form(s)
Operation
Boolean Expression
Addressing
Mode for
Operand
Machine Coding
(Hexadecimal)
Opcode
B
C
Cycle
by
Cycle*
Condition Codes
Operand(s)
S X H I N Z V C
C
b0
b7
C
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