參數(shù)資料
型號： MC68HCP11A1VP2
廠商： MOTOROLA INC
元件分類： 微控制器/微處理器
英文描述： HCMOS Single-Chip Microcontroller
中文描述： 8-BIT, 2 MHz, MICROCONTROLLER, PDIP48
封裝： DIP-48
文件頁數(shù)： 43/158頁
文件大?。?/td> 776K
代理商： MC68HCP11A1VP2
MC68HC11A8
TECHNICAL DATA
PARALLEL I/O
MOTOROLA
4-5
4
STAF — Strobe A Interrupt Status Flag
This bit is set when a selected edge occurs on strobe A. Clearing it depends on the
state of HNDS and OIN bits. In simple strobed mode or in full input handshake mode,
STAF is cleared by reading the PIOC register with STAF set followed by reading the
PORTCL register. In output handshake, STAF is cleared by reading the PIOC register
with STAF set followed by writing to the PORTCL register.
STAI — Strobe A Interrupt Enable Mask
When the I bit in the condition code register is clear and STAI is set, STAF (when set)
will request an interrupt.
CWOM — Port C Wire-OR Mode
CWOM affects all eight port C pins together
0 = Port C outputs are normal CMOS outputs
1 = Port C outputs act as open-drain outputs
HNDS — Handshake Mode
When clear, strobe A acts as a simple input strobe to latch data into PORTCL, and
strobe B acts as a simple output strobe which pulses after a write to port B. When set,
a handshake protocol involving port C, STRA, and STRB is selected (see the definition
for the OIN bit).
0 = Simple strobe mode
1 = Full input or output handshake mode
OIN — Output or Input Handshaking
This bit has no meaning when HNDS = 0.
0 = Input handshake
1 = Output handshake
PLS — Pulse/Interlocked Handshake Operation
This bit has no meaning if HNDS = 0. When interlocked handshake operation is se-
lected, strobe B, once activated, stays active until the selected edge of strobe A is de-
tected. When pulsed handshake operation is selected, strobe B is pulsed for two E
cycles.
0 = Interlocked handshake select
1 = Pulsed handshake selected
EGA — Active Edge for Strobe A
0 = Falling edge of STRA is selected. When output handshake is selected, port C
lines obey the data direction register while STRA is low, but port C is forced to
output when STRA is high.
1 = Rising edge of STRA is selected. When output handshake is selected, port C
lines obey the data direction register while STRA is high, but port C is forced to
output when STRA is low.
INVB — Invert Strobe B
0 = Active level is logic zero
1 = Active level is logic one
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