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參數(shù)資料
| 型號(hào)： | MC68HSC05C12ACP |
| 廠商： | FREESCALE SEMICONDUCTOR INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, MROM, 4.1 MHz, MICROCONTROLLER, PDIP40 |
| 封裝： | PLASTIC, DIP-40 |
| 文件頁(yè)數(shù)： | 132/156頁(yè) |
| 文件大?。?/td> | 3848K |
| 代理商： | MC68HSC05C12ACP |
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Serial Communications Interface (SCI)
SCI I/O Registers
MC68HC05C12A — Rev. 3.0
General Release Specification
Serial Communications Interface (SCI)
NON-DISCLOSURE
AGREEMENT
REQUIRED
bit by reading the SCSR with TC set, and then writing to the SCDR.
Reset sets the TC bit. Software must initialize the TC bit to logic zero
to avoid an instant interrupt request when turning on the transmitter.
1 = No transmission in progress
0 = Transmission in progress
RDRF — Receive Data Register Full
This clearable, read-only bit is set when the data in the receive shift
register transfers to the SCI data register. RDRF generates an
interrupt request if the RIE bit in SCCR2 is also set. Clear the RDRF
bit by reading the SCSR with RDRF set, and then reading the SCDR.
Reset clears the RDRF bit.
1 = Received data available in SCDR
0 = Received data not available in SCDR
IDLE — Receiver Idle
This clearable, read-only bit is set when 10 or 11 consecutive logic
ones appear on the receiver input. IDLE generates an interrupt
request if the ILIE bit in SCCR2 is also set. Clear the IDLE bit by
reading the SCSR with IDLE set, and then reading the SCDR. Reset
clears the IDLE bit.
1 = Receiver input idle
0 = Receiver input not idle
OR — Receiver Overrun
This clearable, read-only bit is set if the SCDR is not read before the
receive shift register receives the next word. OR generates an
interrupt request if the RIE bit in SCCR2 is also set. The data in the
shift register is lost, but the data already in the SCDR is not affected.
Clear the OR bit by reading the SCSR with OR set and then reading
the SCDR. Reset clears the OR bit.
1 = Receiver shift register full and RDRF = 1
0 = No receiver overrun
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For More Information On This Product,
Go to: www.freescale.com
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