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參數(shù)資料
| 型號(hào)： | MC68HSC05C12ACP |
| 廠商： | FREESCALE SEMICONDUCTOR INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, MROM, 4.1 MHz, MICROCONTROLLER, PDIP40 |
| 封裝： | PLASTIC, DIP-40 |
| 文件頁數(shù)： | 145/156頁 |
| 文件大?。?/td> | 3848K |
| 代理商： | MC68HSC05C12ACP |
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Serial Peripiheral Interface (SPI)
SPI Registers
MC68HC05C12A — Rev. 3.0
General Release Specification
Serial Peripiheral Interface (SPI)
NON-DISCLOSURE
AGREEMENT
REQUIRED
WCOL — Write Collision
The write collision bit is set when an attempt is made to write to the
serial peripheral data register while data transfer is taking place. If
CPHA is zero, a transfer is said to begin when SS goes low and the
transfer ends when SS goes high after eight clock cycles on SCK.
When CPHA is one, a transfer is said to begin the first time SCK
becomes active while SS is low. The transfer ends when the SPIF flag
gets set. Clearing the WCOL bit is accomplished by reading the
SPSR (with WCOL set) followed by an access to SPDR.
Bit 5 — Not implemented
This bit always reads as 0.
MODF — Mode Fault
The mode fault flag indicates that there may have been a multi-master
conflict for system control and allows a proper exit from system
operation to a reset or default system state. The MODF bit is normally
clear and is set only when the master device has its SS pin pulled low.
Setting the MODF bit affects the internal serial peripheral interface
system in the following ways:
An SPI interrupt is generated if SPIE = 1.
The SPE bit is cleared. This disables the SPI.
The MSTR bit is cleared, thus forcing the device into the slave
mode.
Clearing the MODF bit is accomplished by reading the SPSR (with
MODF set), followed by a write to the SPCR. Control bits SPE and
MSTR may be restored by user software to their original state after
the MODF bit has been cleared.
Bits 3–0 — Not Implemented
These bits always reads as 0.
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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