參數(shù)資料
型號(hào)： MC68HSC05C12ACP
廠商： FREESCALE SEMICONDUCTOR INC
元件分類： 微控制器/微處理器
英文描述： 8-BIT, MROM, 4.1 MHz, MICROCONTROLLER, PDIP40
封裝： PLASTIC, DIP-40
文件頁數(shù)： 144/156頁
文件大?。?/td> 3848K
代理商： MC68HSC05C12ACP
NON-DISCLOSURE
AGREEMENT
REQUIRED
Serial Peripiheral Interface (SPI)
General Release Specification
MC68HC05C12A — Rev. 3.0
Serial Peripiheral Interface (SPI)
As soon as SS goes low, the transaction begins and the first edge on
SCK invokes the first data sample. When CPHA = 1, the SS pin may
be thought of as a simple output enable control. See Figure 10-1.
SPR1 and SPR0 — SPI Clock Rate Selects
These two bits select one of four baud rates to be used as SCK if the
device is a master; however, they have no effect in the slave mode.
10.6.2 Serial Peripheral Status Register
SPIF — SPI Transfer Complete Flag
The serial peripheral data transfer flag bit is set upon completion of
data transfer between the processor and external device. If SPIF
goes high and if SPIE is set, a serial peripheral interrupt is generated.
Clearing the SPIF bit is accomplished by reading the SPSR (with
SPIF set) followed by an access of the SPDR. Unless SPSR is read
(with SPIF set) first, attempts to write to SPDR are inhibited.
Table 10-1. Serial Peripheral Rate Selection
SPR1
SPR0
Bus Clock Divided By
00
2
01
4
10
16
11
32
Address:
$000B
Bit 7
654321
Bit 0
Read:
SPIF
WCOL
0
MODF
0000
Write:
Reset
000000
U
= Unimplemented
U = Unaffected
Figure 10-5. SPI Status Register (SPSR)
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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