參數(shù)資料
型號: MC68HSC05C8AFN
廠商: MOTOROLA INC
元件分類: 微控制器/微處理器
英文描述: 8-BIT, MROM, 4.1 MHz, MICROCONTROLLER, PQCC44
封裝: PLASTIC, LCC-44
文件頁數(shù): 36/166頁
文件大小: 1914K
代理商: MC68HSC05C8AFN
Electrical Specifications
Technical Data
MC68HC05C8A MC68HCL05C8A MC68HSC05C8A — Rev. 5.0
130
Electrical Specifications
MOTOROLA
Figure 13-5. External Interrupt Timing
Figure 13-6. External Reset Timing
NORMALLY USED
WITH WIRED-OR
CONNECTION
IRQ
tILIH
tILIL
t
ILIH
IRQ PIN
IRQ1
IRQn
.
a. Edge-Sensitive Trigger Condition. The minimum pulse width (tILIH) is either 125 ns (fOP = 2.1 MHz)
or 250 ns (fOP = 1 MHz). The period tILIL should not be less than the number of tCYC cycles it takes to
execute the interrupt service routine plus 19 tCYC cycles.
b. Level-Sensitive Trigger Condition. If after servicing an interrupt the IRQ remains low, the
next interrupt is recognized.
(INTERNAL)
INTERNAL
CLOCK(1)
INTERNAL
ADDRESS BUS(1)
Notes:
INTERNAL
DATA BUS(1)
1FFE
1FFF
NEW PC
1. Internal clock, internal address bus, and internal data bus are not available externally.
2. The next rising edge of the internal clock after the rising edge of RESET initiates the reset sequence.
NEW
PCH
t
RL
NEW
PCL
OP
CODE
RESET(2)
1FFE
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