- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄359147 > MC68HSC05J1A (飛思卡爾半導(dǎo)體(中國)有限公司) Microcontrollers PDF資料下載
參數(shù)資料
| 型號： | MC68HSC05J1A |
| 廠商： | 飛思卡爾半導(dǎo)體(中國)有限公司 |
| 英文描述： | Microcontrollers |
| 中文描述： | 微控制器 |
| 文件頁數(shù)： | 38/128頁 |
| 文件大小： | 1620K |
| 代理商： | MC68HSC05J1A |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁當(dāng)前第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁第72頁第73頁第74頁第75頁第76頁第77頁第78頁第79頁第80頁第81頁第82頁第83頁第84頁第85頁第86頁第87頁第88頁第89頁第90頁第91頁第92頁第93頁第94頁第95頁第96頁第97頁第98頁第99頁第100頁第101頁第102頁第103頁第104頁第105頁第106頁第107頁第108頁第109頁第110頁第111頁第112頁第113頁第114頁第115頁第116頁第117頁第118頁第119頁第120頁第121頁第122頁第123頁第124頁第125頁第126頁第127頁第128頁
Technical Data
MC68HC05J1A — Rev. 3.0
38
Central Processor Unit (CPU)
For More Information On This Product,
Go to: www.freescale.com
MOTOROLA
Central Processor Unit (CPU)
3.3.5 Condition Code Register
The condition code register (CCR) shown in
Figure 3-6
is an 8-bit
register whose three most significant bits are permanently fixed at 111.
The condition code register contains the interrupt mask and four flags
that indicate the results of prior instructions.
H — Half-Carry Flag
The CPU sets the half-carry flag when a carry occurs between bits 3
and 4 of the accumulator during an add without carry (ADD) or add
with carry (ADC) operation. The half-carry bit is required for
binary-coded decimal (BCD) arithmetic operations. Reset has no
effect on the half-carry flag.
I — Interrupt Mask Flag
Setting the interrupt mask (I) disables interrupts. If an interrupt
request occurs while the interrupt mask is a logic 0, the CPU saves
the CPU registers on the stack, sets the interrupt mask, and then
fetches the interrupt vector. If an interrupt request occurs while the
interrupt mask is set, the interrupt request is latched. The CPU
processes the latched interrupt as soon as the interrupt mask is
cleared again.
A return-from-interrupt (RTI) instruction pulls the CPU registers from
the stack, restoring the interrupt mask to its cleared state. After a
reset, the interrupt mask is set and can be cleared only by a clear
interrupt mask bit (CLI), STOP, or WAIT instruction.
Bit 7
6
5
4
3
2
1
Bit 0
Read:
1
1
1
H
I
N
Z
C
Write:
Reset:
1
1
1
U
1
U
U
U
= Unimplemented
U = Unaffected
Figure 3-6. Condition Code Register (CCR)
F
Freescale Semiconductor, Inc.
n
.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| MC68SZ328 | i.MX Integrated Portable System Processor |
| MC72000 | Integrated Bluetooth Radio |
| MC7445ARX1000LF | RISC Microprocessor Hardware Specifications |
| MC7445ARX1000LG | RISC Microprocessor Hardware Specifications |
| MC7447A | PowerPC microprocessor |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MC68HSC705C8ACFB | 制造商:Rochester Electronics LLC 功能描述:8 BIT MCU, 304 BYTES RAM - Bulk |
| MC68HSC705C8ACP | 制造商:Rochester Electronics LLC 功能描述: 制造商:Freescale Semiconductor 功能描述: |
| MC68HSC705C8ACS | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| MC68HSC705J1ACDW | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| MC68HSC705J1ACP | 制造商:Rochester Electronics LLC 功能描述:8 BIT MCU, 64 BYTES RAM - Bulk |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。