參數(shù)資料
型號： MC68HSC05J1A
廠商： 飛思卡爾半導(dǎo)體(中國)有限公司
英文描述： Microcontrollers
中文描述： 微控制器
文件頁數(shù)： 93/128頁
文件大?。?/td> 1620K
代理商： MC68HSC05J1A
Instruction Set
Opcode Map
MC68HC05J1A — Rev. 3.0
Technical Data
MOTOROLA
Instruction Set
93
9.6 Opcode Map
See
Table 9-7
.
TST
opr
TSTA
TSTX
TST
opr
,X
TST ,X
Test Memory Byte for Negative or Zero
(M) – $00
— —
—
DIR
INH
INH
IX1
IX
3D
4D
5D
6D
7D
dd
ff
4
3
3
5
4
TXA
Transfer Index Register to Accumulator
A
←
(X)
— — — — —
INH
9F
2
WAIT
Stop CPU Clock and Enable Interrupts
— 0 — — —
INH
8F
2
A
C
CCR
dd
dd rr
DIR
ee ff
EXT
ff
H
hh ll
I
ii
IMM
INH
IX
IX1
IX2
M
N
n
Accumulator
Carry/borrow flag
Condition code register
Direct address of operand
Direct address of operand and relative offset of branch instruction
Direct addressing mode
High and low bytes of offset in indexed, 16-bit offset addressing
Extended addressing mode
Offset byte in indexed, 8-bit offset addressing
Half-carry flag
High and low bytes of operand address in extended addressing
Interrupt mask
Immediate operand byte
Immediate addressing mode
Inherent addressing mode
Indexed, no offset addressing mode
Indexed, 8-bit offset addressing mode
Indexed, 16-bit offset addressing mode
Memory location
Negative flag
Any bit
opr
PC
PCH
PCL
REL
rel
rr
SP
X
Z
#
∧
∨
⊕
( )
–( )
←
:
Operand (one or two bytes)
Program counter
Program counter high byte
Program counter low byte
Relative addressing mode
Relative program counter offset byte
Relative program counter offset byte
Stack pointer
Index register
Zero flag
Immediate value
Logical AND
Logical OR
Logical EXCLUSIVE OR
Contents of
Negation (two’s complement)
Loaded with
If
Concatenated with
Set or cleared
Not affected
—
Table 9-6. Instruction Set Summary (Sheet 6 of 6)
Source
Form
Operation
Description
Effect
on CCR
A
M
O
O
C
H I N Z C
F
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
n
.
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