MOTOROLA
M68040 USER’S MANUAL
xix
LIST OF ILLUSTRATIONS (Continued)
Figure
Number
Page
Number
Title
7-26
7-27
7-28
7-29
7-30
Word Write Access Terminated with
TEA
Timing ........................................
Line Read Access Terminated with
TEA
Timing ..........................................
Retry Read Transfer Timing .........................................................................
Retry Operation on Line Write......................................................................
M68040 Internal Interpretation State Diagram and
External Bus Arbiter Circuit ........................................................................
Lock Violation Example................................................................................
Processor Bus Request Timing....................................................................
Arbitration During Relinquish and Retry Timing ...........................................
Implicit Bus Ownership Arbitration Timing....................................................
Dual M68040 Fairness Arbitration State Diagram........................................
Dual M68040 Prioritized Arbitration State Diagram .....................................
M68040 Synchronous DMA Arbitration........................................................
Sample Synchronizer Circuit........................................................................
M68040 Asynchronous DMA Arbitration ......................................................
Snoop-Inhibited Bus Cycle...........................................................................
Snoop Access with Memory Response........................................................
Snooped Line Read, Memory Inhibited........................................................
Snooped Long-Word Write, Memory Inhibited .............................................
Initial Power-On Reset Timing......................................................................
Normal Reset Timing ...................................................................................
Multiplexed Address and Data Bus (Line Write)...........................................
DLE Mode Block Diagram............................................................................
DLE versus Normal Data Read Timing........................................................
7-39
7-40
7-41
7-42
7-47
7-49
7-50
7-51
7-52
7-53
7-55
7-56
7-57
7-58
7-61
7-62
7-64
7-65
7-66
7-67
7-69
7-70
7-71
7-31
7-32
7-33
7-34
7-35
7-36
7-37
7-38
7-39
7-40
7-41
7-42
7-43
7-44
7-45
7-46
7-47
7-48
8-1
8-2
8-3
8-4
8-5
8-6
8-7
8-8
General Exception Processing Flowchart ....................................................
General Form of Exception Stack Frame.....................................................
Interrupt Recognition Examples ...................................................................
Interrupt Exception Processing Flowchart....................................................
Reset Exception Processing Flowchart........................................................
Flowchart of RTE Instruction for Throwaway Four-Word Frame..................
Special Status Word Format ........................................................................
Write-Back Status Format ............................................................................
8-3
8-4
8-14
8-16
8-18
8-22
8-24
8-26
9-1
9-2
9-3
9-4
9-5
9-6
9-7
9-8
Floating-Point User Programming Model.....................................................
Floating-Point Control Register....................................................................
FPSR Condition Code Byte..........................................................................
FPSR Quotient Byte.....................................................................................
FPSR Exception Status Byte .......................................................................
FPSR Accrued Exception Byte ....................................................................
Intermediate Result Format..........................................................................
Rounding Algorithm Flowchart .....................................................................
9-2
9-4
9-4
9-5
9-5
9-6
9-12
9-14