
MOTOROLA
M68040 USER’S MANUAL
1-17
Table 1-4. Instruction Set Summary (Continued)
Opcode
FNEG2
Operation
Syntax
–(Source)
FPn
FNEG.<fmt> <ea>,FPn
FNEG.X FPm,FPn
FNEG.X FPn
FrNEG.<fmt> <ea>,FPn3
FrNEG.X FPm,FPn3
FrNEG.X FPn3
FNOP2
FRESTORE2
None
FNOP
If in supervisor state
then FPU State Frame
Internal State
else TRAP
FRESTORE <ea>
FSAVE2
If in supervisor state
then FPU Internal State
State Frame
else TRAP
FSAVE <ea>
FScc2
If condition true
then 1s
Destination
else 0s
Destination
FScc.SIZE <ea>
FSGLDIV
FPn
÷
Source
FPn
FSGLDIV.<fmt> <ea>,FPn
FSGLDIV.X FPm,FPn
FSGLMUL
Source
×
FPn
FPn
FSGMUL.<fmt> <ea>,FPn
FSGLMUL.X FPm, FPn
FSQRT2
Square Root of Source
FPn
FSQRT.<fmt> <ea>,FPn
FSQRT.X FPm,FPn
FSQRT.X FPn
FrSQRT.<fmt> <ea>,FPn3
FrSQRT FPm,FPn3
FrSQRT FPn3
FSUB2
FPn – Source
FPn
FSUB.<fmt> <ea>,FPn
FSUB.X FPm,FPn
FrSUB.<fmt> <ea>,FPn3
FrSUB.X FPm,FPn3
FTRAPcc2
If condition true
then TRAP
FTRAPcc
FTRAPcc.W #<data>
FTRAPcc.L #<data>
FTST2
Condition Codes for Operand
FPCC
FTST.<fmt> <ea>
FTST.X FPm
ILLEGAL
SSP – 2
SSP; Vector Offset
(SSP);
SSP – 4
SSP; PC
(SSP);
SSp – 2
SSP; SR
(SSP);
Illegal Instruction Vector Address
PC
ILLEGAL
JMP
Destination Address
PC
JMP <ea>
JSR
SP – 4
SP; PC
(SP)
Destination Address
PC
JSR <ea>
LEA
<ea>
An
LEA <ea>,An
LINK
SP – 4
SP; An
(SP)
SP
An, SP+d
SP
LINK An,dn