viii
M68040 USER’S MANUAL
MOTOROLA
TABLE OF CONTENTS (Continued)
Paragraph
Number
Page
Number
Title
Section 4
Instruction and Data Caches
4.1
4.2
4.3
4.3.1
4.3.1.1
4.3.1.2
4.3.2
4.3.3
4.4
4.4.1
4.4.2
4.4.3
4.4.4
4.5
4.6
4.6.1
4.6.2
4.7
4.7.1
4.7.2
Cache Operation...................................................................................
Cache Management..............................................................................
Caching Modes .....................................................................................
Cachable Accesses...........................................................................
Write-Through Mode ......................................................................
Copyback Mode.............................................................................
Cache-Inhibited Accesses.................................................................
Special Accesses ..............................................................................
Cache Protocol .....................................................................................
Read Miss .........................................................................................
Write Miss..........................................................................................
Read Hit ............................................................................................
Write Hit.............................................................................................
Cache Coherency .................................................................................
Memory Accesses for Cache Maintenance...........................................
Cache Filling......................................................................................
Cache Pushes...................................................................................
Cache Operation Summary...................................................................
Instruction Cache...............................................................................
Data Cache........................................................................................
4-2
4-5
4-6
4-6
4-6
4-6
4-7
4-7
4-7
4-8
4-8
4-8
4-8
4-9
4-11
4-11
4-13
4-13
4-14
4-15
Section 5
Signal Description
5.1
5.2
5.3
5.3.1
5.3.2
5.3.3
5.3.4
5.3.5
5.3.6
5.3.7
5.3.8
5.3.9
5.4
5.4.1
Address Bus (A31–A0) .........................................................................
Data Bus (D31–D0)...............................................................................
Transfer Attribute Signals......................................................................
Transfer Type (TT1, TT0)..................................................................
Transfer Modifier (TM2–TM0) ...........................................................
Transfer Line Number (TLN1, TLN0).................................................
User-Programmable Attributes (UPA1, UPA0)..................................
Read/Write (R/
W
) ..............................................................................
Transfer Size (SIZ1, SIZ0) ................................................................
Lock (
LOCK
) ......................................................................................
Lock End (
LOCKE
) ............................................................................
Cache Inhibit Out (
CIOUT
) ................................................................
Bus Transfer Control Signals ................................................................
Transfer Start (
TS
).............................................................................
5-4
5-5
5-5
5-5
5-6
5-6
5-7
5-7
5-7
5-7
5-7
5-8
5-8
5-8