參數(shù)資料
型號： MC68LC060RC66
廠商： Freescale Semiconductor
文件頁數(shù)： 34/128頁
文件大?。?/td> 0K
描述： IC MPU 32BIT 66MHZ 206-PGA
標準包裝： 10
系列： M680x0
處理器類型： M680x0 32-位
速度： 66MHz
電壓： 3.3V
安裝類型： 通孔
封裝/外殼： 206-BEPGA
供應商設(shè)備封裝： 206-PGA（47.25x47.25）
包裝： 托盤
Table of Contents
MOTOROLA
M68060 USER’S MANUAL
xv
8.3
Exception Priorities ..................................................................................... 8-17
8.4
Return from Exceptions .............................................................................. 8-19
8.4.1
Four-Word Stack Frame (Format $0) ....................................................... 8-19
8.4.2
Six-Word Stack Frame (Format $2) .......................................................... 8-20
8.4.3
Floating-Point Post-Instruction Stack Frame (Format $3) ........................ 8-20
8.4.4
Eight-Word Stack Frame (Format $4)....................................................... 8-21
8.4.4.1
Program Counter (PC)............................................................................ 8-21
8.4.4.2
Fault Address ......................................................................................... 8-22
8.4.4.3
Fault Status Long Word (FSLW)............................................................. 8-22
8.4.5
Recovering from an Access Error ............................................................. 8-25
8.4.6
Bus Errors and Pending Memory Writes ................................................. 8-27
8.4.7
Branch Prediction Error ............................................................................ 8-29
Section 9
IEEE 1149.1 Test (JTAG) and Debug Pipe Control Modes
9.1
IEEE 1149.1 Test Access Port (Normal JTAG) Mode .................................. 9-1
9.1.1
Overview ..................................................................................................... 9-2
9.1.2
JTAG Instruction Shift Register .................................................................. 9-3
9.1.2.1
EXTEST.................................................................................................... 9-4
9.1.2.2
LPSAMPLE............................................................................................... 9-5
9.1.2.3
Private Instructions ................................................................................... 9-5
9.1.2.4
SAMPLE/PRELOAD ................................................................................. 9-5
9.1.2.5
IDCODE.................................................................................................... 9-5
9.1.2.6
CLAMP ..................................................................................................... 9-6
9.1.2.7
HIGHZ....................................................................................................... 9-6
9.1.2.8
BYPASS ................................................................................................... 9-6
9.1.3
JTAG Test Data Registers .......................................................................... 9-7
9.1.3.1
Idcode Register ........................................................................................ 9-7
9.1.3.2
Boundary Scan Register........................................................................... 9-7
9.1.3.3
Bypass Register ..................................................................................... 9-15
9.1.4
Restrictions ............................................................................................... 9-15
9.1.5
Disabling the IEEE 1149.1 Standard Operation ....................................... 9-15
9.1.6
Motorola MC68060 BSDL Description ...................................................... 9-17
9.2
Debug Pipe Control Mode........................................................................... 9-24
9.2.1
Debug Command Interface....................................................................... 9-25
9.2.2
Debug Pipe Control Mode Commands ..................................................... 9-27
9.2.3
Emulator Mode ......................................................................................... 9-31
9.3
Switching between JTAG and Debug Pipe ControlModes of Operation..... 9-33
Section 10
Instruction Execution Timing
10.1
Superscalar Operand Execution Pipelines ................................................. 10-1
10.1.1
Dispatch Test 1: sOEP Opword and Required
Extension Words Are Valid ....................................................................... 10-2
10.1.2
Dispatch Test 2: Instruction Classification ................................................ 10-2
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