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| 型號： | MC68LC060RC66 |
| 廠商： | Freescale Semiconductor |
| 文件頁數(shù)： | 83/128頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC MPU 32BIT 66MHZ 206-PGA |
| 標準包裝： | 10 |
| 系列： | M680x0 |
| 處理器類型： | M680x0 32-位 |
| 速度： | 66MHz |
| 電壓： | 3.3V |
| 安裝類型： | 通孔 |
| 封裝/外殼： | 206-BEPGA |
| 供應商設備封裝： | 206-PGA（47.25x47.25） |
| 包裝： | 托盤 |
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Signal Description
2-12
M68060 USER’S MANUAL
MOTOROLA
The MC68060 provides the BB signal and protocol to provide compatibility with MC68040-
style buses. Either the BTT signal and protocol or the BB signal and protocol (but not both)
should be used. The unused signal, either BTT or BB, must be pulled up with a pullup resis-
tor and tied to VCC. Use of the BTT signal and protocol yields higher performance at full bus
speed and high operating frequencies. The use of BB and its associated protocol is not rec-
ommended at full bus speeds. The BTT protocol is discussed in detail in Section 7 Bus Op-
eration.
2.7.5 Bus Busy (BB)
This three-state bidirectional signal indicates that the bus is currently owned. BB is moni-
tored as a processor input to determine when an alternate bus master has released control
of the bus. The MC68060 samples bus availability on each clock-enabled clock edge. BG
must be asserted and both TS and BB must be negated (indicating the bus is free) before
the MC68060 asserts BB (with the first assertion of TS) as an output to assume ownership
of the bus. The processor keeps BB asserted until the external arbiter negates BG and the
processor completes the bus cycle in progress. When releasing the bus, the processor
negates BB for one clock period, then places it in a high-impedance state and begins to
sample it as an input. Note that the one clock period in which BB is negated is one MC68060
processor clock period, not a full clock-enabled clock period.
The MC68060 provides the BB signal and protocol to support compatibility with MC68040-
style buses. Either the BTT signal and protocol or the BB signal and protocol (but not both)
should be used. The unused signal, either BTT or BB, must be pulled up through a pullup
resistor and tied to VCC. Use of the BTT signal and protocol yields higher performance at full
bus speed and high operating frequencies. The use of BB and its associated protocol is not
recommended at full bus speeds. The BTT protocol is discussed in detail in Section 7 Bus
Operation.
2.8 PROCESSOR CONTROL SIGNALS
The following signals control the caches and MMUs and support processor and external
device initialization.
2.8.1 Cache Disable (
CDIS)
When asserted, this input signal dynamically disables the on-chip caches on the next inter-
nal cache access boundary. The caches are enabled on the next boundary after CDIS is
negated.
CDIS does not flush the data and instruction caches. Cache entries remain unaltered and
become available after CDIS is negated, unless one of the cache invalidate instructions
(CINVA, CINVP, CINVL) are executed. The execution of one of the cache invalidate instruc-
tions may invalidate entries even if the caches have been disabled with this signal. The
assertion of CDIS does not affect snooping.
Refer to Section 5 Caches for information about the caches.
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