參數(shù)資料
型號： MC68MH360ZQ25L
廠商： Freescale Semiconductor
文件頁數(shù)： 130/158頁
文件大小： 0K
描述： IC MPU QUICC 25MHZ 357-PBGA
標(biāo)準(zhǔn)包裝： 44
系列： M683xx
處理器類型： M683xx 32-位
速度： 25MHz
電壓： 5V
安裝類型： 表面貼裝
封裝/外殼： 357-BBGA
供應(yīng)商設(shè)備封裝： 357-PBGA（25x25）
包裝： 托盤
Chapter 5. Buffer Descriptors
Figure 5-2 shows how non-octet alignment is reported and how data is stored. The two
diagrams on the left show the reception of a single-buffer, 12-byte frame including the
CRC. In the top case, the reception is correctly octet-aligned and the frame length indicates
12 bytes.
11
NO
Rx non-octet-aligned frame (HDLC mode only)—A frame that contained a number of bits not
exactly divisible by eight was received. NO = 1 for any type of nonalignment regardless of frame
length. The shortest frame that can be detected is of type Flag-Bit-Flag. This causes the buffer to
be closed with the NO error indicated.
Figure 5-2 shows how the non-octet alignment is reported and where data can be found.
12
AB
Rx abort sequence—A minimum of seven consecutive ones was received during frame
reception. Abort is not detected between frames. The sequence ...closing-ag, data, CRC, ag,
AB, ag, data, opening-ag... does not cause an abort error. If the abort is long enough to be an
idle, an idle line interrupt may be generated. An abort within the frame is not reported by a unique
interrupt but rather with an RXF interrupt; the user has to examine the buffer descriptor.
13
CR
Rx CRC error—This frame contains a CRC error. The received CRC bytes are always written to
the receive buffer.
14–15
—
16–31
DL
Data length—the number of octets written by the CPM into this buffer descriptor’s data buffer. It is
written by the CPM once when the buffer descriptor is closed.
When this buffer descriptor is the last buffer descriptor of a frame (L = 1), the data length equals
the total number of octets in the frame (including the two- or four-byte CRC).
Note: The amount of memory allocated for this buffer should be greater than or equal to the
contents of the maximum receive buffer length register (MRBLR + 4).
32–63
RxBP
Rx buffer pointer—The receive buffer pointer, which always points to the rst location of the
associated data buffer, may reside in either internal or external memory. The Rx buffer pointer
must be divisible by 4.
Table 5-1. Receive Buffer Descriptor (RxBD) Field Descriptions (Continued)
Field
Name
Description
F
re
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S
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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