參數(shù)資料
型號(hào)： MC68MH360ZQ25L
廠商： Freescale Semiconductor
文件頁數(shù)： 19/158頁
文件大?。?/td> 0K
描述： IC MPU QUICC 25MHZ 357-PBGA
標(biāo)準(zhǔn)包裝： 44
系列： M683xx
處理器類型： M683xx 32-位
速度： 25MHz
電壓： 5V
安裝類型： 表面貼裝
封裝/外殼： 357-BBGA
供應(yīng)商設(shè)備封裝： 357-PBGA（25x25）
包裝： 托盤
Chapter 8.Performance
8.3 Bus Latency and Peak Load
Each time slot is 8 bits, but the QMC protocol transfers 32 bits of data whenever possible.
Thus, for each active channel operating within large frames, two 32-bit SDMA data
transfers (one for Tx and one for Rx) occur approximately every fourth TDM frame (every
500
s in CEPT/T1 interfaces). During buffer closing or opening, load will increase
approximately 3 to 4 times. Table 8-3 illustrates the bus activities involved when one QMC
channel switches from one Tx HDLC frame to the next.
Note: The table assumes the channel uses one time slot per TDM frame and that no PAD characters,
preceding ags or ag sharing is used.
In Table 8-3, the frame number refers to the 125-
s frame; the numbering is arbitrary but
sequential. The actions refer to the visible functions executed on the CPM. The number of
external bus cycles executed by the CPM represents the load on the bus.
The sequence in Table 8-3 starts when the last 32 bits are read from a buffer. One byte is
transferred over the TDM link per frame over the next four 125-
s frames. Then the CRC
is sent. In this case, it is a 16-bit CRC requiring two time slots over the next two frames.
The heavy load on the bus starts when the CPM must close the buffer in frame 8. At this
point the CPM needs three accesses to the bus to read and write to the interrupt table and
update the buffer descriptor’s status. In the following frame, the next buffer is opened
requiring three accesses to read the status and length, read the data pointer and read the data.
Table 8-3. QMC Actions in Tx Buffer Switch
Frame
Number
Actions
Number of
Bus Cycles
1
Read long word from buffer
(last in frame)
1
2
Send byte
0
3
Send byte
0
4
Send byte
0
5
Send last byte in frame
0
6
Send CRC
0
7
Send CRC
0
8
Send ag
Read interrupt table
Write interrupt table
Write BD
3
9
Send ag
Read next BD status/length
Read BD data pointer
Read data
3
10
Send rst byte of next frame
0
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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