參數(shù)資料
型號(hào)： MC68MH360ZQ25LR2
廠商： Freescale Semiconductor
文件頁數(shù)： 15/158頁
文件大?。?/td> 0K
描述： IC MPU QUICC 25MHZ 357-PBGA
標(biāo)準(zhǔn)包裝： 180
系列： M683xx
處理器類型： M683xx 32-位
速度： 25MHz
電壓： 5V
安裝類型： 表面貼裝
封裝/外殼： 357-BBGA
供應(yīng)商設(shè)備封裝： 357-PBGA（25x25）
包裝： 帶卷 (TR)
Chapter 8.Performance
Chapter 8
Performance
80
Calculating performance is key to choosing the clock frequency required for a given
system. For the 860MH and MH360, the large number of possible channel combinations
complicates performance estimation.
This chapter addresses the problem by rst providing a performance table for common
congurations supported by the 860MH and/or the MH360 in Section 8.1, “Common
Channel Combinations.” For congurations not covered in the rst section, Section 8.2,
“CPM Loading,” covers general guidelines and examples for determining the serial bit rate
and CPM loading on a given system. The nal section, Section 8.3, “Bus Latency and Peak
Load,” addresses system bus utilization and arbitration.
For more denitive answers to performance questions, benchmark the desired
conguration on a development board.
8.1 Common Channel Combinations
Table 8-1 provides some common channel combinations congured on the MH devices
along with suggested operating frequencies. Note that the MH360 is available only at 25
and 33 MHz,; the 860MH is currently available at 25, 40, and 50 MHz.
Table 8-1. Common QMC Configurations
Protocols Selected
Frequency Supported
25 MHz
33 MHz
40 MHz
50 MHz
SCC1: 24-channel QMC. Serial bit rate 1.544 Mbps (T1)
Yes
SCC1: 32-channel QMC.
Serial bit rate 2.048 Mbps (E1/CEPT)
Yes
SCC1: 10-Mbps Ethernet; SCC2: 12 x 64-Kbps QMC;
SCC3: 12 x 64-Kbps QMC. TDM bit rate = 1.544 Mbps
Yes
SCC1: 10-Mbps Ethernet; SCC2: 16 x 64-Kbps QMC;
TDM bit rate = 1.544 Mbps
Yes
SCC1: 32 x 64-Kbps QMC; SCC2: 64 Kbps;
SCC3:64 Kbps; SCC4: 64 Kbps; all HDLC.
Yes
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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