參數(shù)資料
型號(hào): MC68MH360ZQ25LR2
廠商: Freescale Semiconductor
文件頁數(shù): 91/158頁
文件大?。?/td> 0K
描述: IC MPU QUICC 25MHZ 357-PBGA
標(biāo)準(zhǔn)包裝: 180
系列: M683xx
處理器類型: M683xx 32-位
速度: 25MHz
電壓: 5V
安裝類型: 表面貼裝
封裝/外殼: 357-BBGA
供應(yīng)商設(shè)備封裝: 357-PBGA(25x25)
包裝: 帶卷 (TR)
QMC Supplement
NOTE
The area between SCC base + 20 and SCC base + 9F is
normally used for TSA tables. The mapping above is ideal for
32-channel support. The exact mapping of the TSA tables is
determined
by
the
programming
of
Rx_S_PTR
and
Tx_S_PTR, and is not xed. For 64-channel support it is
suggested to use common Rx and Tx parameters. The TSA
table will be common and have 64 entries starting at SCC base
+ 20; see Figure 2-4. Alternatively, another SCC’s parameter
RAM may be used, as determined by Rx_S_PTR and
Tx_S_PTR; see Figure 2-6 for more information. However
implemented, the TSA tables may reside anywhere in internal
memory.
Figure 2-3 shows a general time slot assignment table for 32 16-bit time slots. The elds
will be used to either transmit or receive channels.
Figure 2-3. Time Slot Assignment Table
Channel Pointer
W
V
Time Slot 0
Time Slot 1
Time Slot 30
Time Slot 31
32 x 16
Mask(2:7)
Mask(0:1)
Channel Pointer
W
V
Mask(2:7)
Mask(0:1)
Channel Pointer
W
V
Mask(2:7)
Mask(0:1)
Channel Pointer
W
V
Mask(2:7)
Mask(0:1)
Channel Pointer
W
V
Mask(2:7)
Mask(0:1)
Channel Pointer
W
V
Mask(2:7)
Mask(0:1)
Channel Pointer
W
V
Mask(2:7)
Mask(0:1)
Note: For the 68360, the bit numbering is reversed. See Appendix A for more information.
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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