參數(shù)資料
型號: MC68QH302
廠商: Motorola, Inc.
英文描述: 32-Bit Microprocessor(32位微處理器)
中文描述: 32位微處理器(32位微處理器)
文件頁數(shù): 11/50頁
文件大小: 6613K
代理商: MC68QH302
2
MC68QH302 Supplement to the MC68302 Users Manual
MOTOROLA
For external-active ISDN terminal adaptor applications, SCC1 supports both B channels
(B1 and B2), and SCC3 handles the D channel. SCC2 is thus free to carry a UART host
interface, eliminating the need for host-interface glue logic. Figure 2 shows the
implementation of a full ISDN basic rate interface using the QH302.
Figure 2. Full ISDN Basic Rate Interface Using the QH302
In non-QH mode, the QH302 can be used in standard 302 applications as well. Note that
the QH302 SCC parameter RAM mapping has been modiTed requiring corresponding
adjustments in the conTguration software. See Section 2.7, òNon-QH Channel Parameter
RAM.ó
1.2 Features
Main features of the QH302 and changes relative to the standard 302 follow:
Supports two independent communications channels using SCC1
Allows independent connection/disconnection for individual B channels
Supports HDLC and totally transparent protocols for individual B channels
Allows independent transmit and receive bit-masking for both B channels
Allows exible buffer descriptor table placement using the new base address
parameters, RBASE and TBASE
Allows RAM microcode packages
Enables software to distinguish a QH302 from a 302 by use of a revision number
Supports special host commands for the individual B channels
Supports a 64-
m
s (or longer) DRAM refresh cycle in QH mode
Host
PC
SCC1: QH
SCC3: HDLC
B1 + B2
D
SI
SCC2: UART
MC68QH302
IDL/GCI
SCP
S/T or U
ISDN Line
Transceiver
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