參數(shù)資料
型號(hào)： MC68QH302
廠(chǎng)商： Motorola, Inc.
英文描述： 32-Bit Microprocessor(32位微處理器)
中文描述： 32位微處理器（32位微處理器）
文件頁(yè)數(shù)： 36/50頁(yè)
文件大?。?/td> 6613K
代理商： MC68QH302
MOTOROLA
MC68QH302 Supplement to the MC68302 Users Manual
27
2.11 QH302 Rx Buffer Descriptors for
HDLC/Transparent Mode
The receiver uses the Rx buffer descriptor to report information about the received data.
Figure 24 shows the status-and-control word. Table 27 describes the status-and-control bit
Telds.
Figure 24. Rx Buffer Descriptor Status and Control
Table 26. Tx Status and Control Field Descriptions
Bit(s)
Name
Description
15
R
1
Ready
0 =The data buffer is not ready for sending. Cleared by the transmitter after the buffer has been
fully sent or an error condition occurs.
1=The data buffer is ready for sending, but has not yet been fully sent. The host should not
modify any field of this BD after setting this bit.
14
—
Reserved
13
W
1
Wrap
0 = Not the last BD in the Tx BD table.
1 = The last BD in the Tx BD table.
12
I
1
Interrupt.
0 = No TXB interrupt is generated after this buffer was transmitted.
1= The TXB bit in the event register (SCCE) will be set.
11
L
1
Last
0 = Not the last buffer in the frame.
1 = The last buffer in the frame.
10
TC
1
Transmit CRC. Valid only when the last (L) bit is set.
0 = Do not send CRC after the last byte is sent.
1 = Send the CRC after the last byte is sent.
9–2
—
Reserved
1
UN
2
Underrun. A transmitter underrun occurred. Not set for B channels.
0
CT
2
Clear-to-send lost. The CTS for an NMSI channel, or L1GR (layer-1 grant) in IDL/GCI for the D
channel, was lost during frame transmission.
Notes:
1
Written by the user before the buffer is sent
2
Status flag set by the transmitter after the entire data buffer has been sent
15
E
14
—
13
W
12
I
11
L
10
F
9
—
8
—
7
—
6
—
5
—
4
3
2
1
0
+0
NO
AB
CR
OV
CD
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