參數(shù)資料
型號(hào): MC68QH302
廠商: Motorola, Inc.
英文描述: 32-Bit Microprocessor(32位微處理器)
中文描述: 32位微處理器(32位微處理器)
文件頁(yè)數(shù): 42/50頁(yè)
文件大?。?/td> 6613K
代理商: MC68QH302
MOTOROLA
MC68QH302 Supplement to the MC68302 Users Manual
33
2.15 QH302 HDLC Differences
The QH302 HDLC protocol does not support the following:
Address recognition (no SCC data synchronization register (DSR))
Error statistics counters
Checking of frames that are too long (MFLR).
Additional differences are as follows:
Non-octet framethe last 16 data bits of non-octet frame may be corrupted.
The data-length word of the last Rx buffer descriptor in frame contains the length of
the last buffer only.
IDL/CTS/CD interrupts are not supported for either B channel but are supported for
the QH-HDLC protocol.
Host commands for the B channels can only enable/disable the Rx/Tx channels; see
Section 2.13, òChannel Host Commands.ó
ENTER
HUNT
MODE
does not exist for the B channels. Instead, the user must
STOP
RX
,
update parameters, and then
RESTART
RX
.
After executing a
STOP
TX
instruction for either B channel, the channel enters idle
mode until the
RESTART
TX
instruction is executed.
Table 35. Parameters to be Initialized before Every
RESTART
RX
Parameter Name
HDLC Mode Value
Transparent Mode Value
R_F_STAT
For B1: 0x0000
For B2: 0x0020
For B1: 0x02C0
For B2: 0x02E0
R_F_POST
0x00
R_F_PRE
0x00
RSTATE
See Section 2.6.1, “RSTATE—Receive Internal State.”
RFCR
See Section 2.6.10, “TFCR and RFCR—Data Buffer Function Code Registers.”
RBASE
See Section 2.6.8, “RBASE and TBASE—Descriptor Table Base Addresses.”
RBDPTR
See Section 2.6.9, “TBDPTR and RBDPTR—Tx/Rx Buffer Descriptor Pointers.”
MRBLR
See Section 2.6.11, “MRBLR—Maximum Receive Buffer Length Register.”
C_MASK_L/H
See Section 2.6.12, “C_MASK_L/H—Constant for CRC Check.”
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