參數(shù)資料
型號: MC68SZ328
廠商: 飛思卡爾半導(dǎo)體(中國)有限公司
英文描述: i.MX Integrated Portable System Processor
中文描述: i.MX處理器集成的便攜式系統(tǒng)
文件頁數(shù): 63/96頁
文件大小: 1495K
代理商: MC68SZ328
Specifications
MC9328MX1 Advance Information, Rev. 4
Freescale Semiconductor
63
Table 28. 4/8/16 Bit/Pixel TFT Color Mode Panel Timing Table
Symbol
Description
Minimum
Corresponding Register Value
Unit
T1
End of OE to beginning of VSYN
T5+T6
+T7+T9
(VWAIT1·T2)+T5+T6+T7+T9
Ts
T2
HSYN period
XMAX+5
XMAX+T5+T6+T7+T9+T10
Ts
T3
VSYN pulse width
T2
VWIDTH·(T2)
Ts
T4
End of VSYN to beginning of OE
2
VWAIT2·(T2)
Ts
T5
HSYN pulse width
1
HWIDTH+1
Ts
T6
End of HSYN to beginning to T9
1
HWAIT2+1
Ts
T7
End of OE to beginning of HSYN
1
HWAIT1+1
Ts
T8
SCLK to valid LD data
-3
3
ns
T9
End of HSYN idle2 to VSYN edge
(for non-display region)
2
2
Ts
T9
End of HSYN idle2 to VSYN edge
(for Display region)
1
1
Ts
T10
VSYN to OE active (Sharp = 0),
when VWAIT2 = 0
1
1
Ts
T10
VSYN to OE active (Sharp = 1),
when VWAIT2 = 0
2
2
Ts
Note:
Ts is the SCLK period which equals LCDC_CLK / (PCD + 1). Normally LCDC_CLK = 15ns.
VSYN, HSYN and OE can be programmed as active high or active low. In Figure 46, all 3 signals are active low.
The polarity of SCLK and LD[15:0] can also be programmed.
SCLK can be programmed to be deactivated during the VSYN pulse or the OE deasserted period. In Figure 46, SCLK is
always active.
For T9 non-display region, VSYN is non-active. It is used as an reference.
XMAX is defined in pixels.
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