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參數(shù)資料
| 型號： | MC68SZ328 |
| 廠商： | 飛思卡爾半導(dǎo)體(中國)有限公司 |
| 英文描述： | i.MX Integrated Portable System Processor |
| 中文描述： | i.MX處理器集成的便攜式系統(tǒng) |
| 文件頁數(shù)： | 88/96頁 |
| 文件大?。?/td> | 1495K |
| 代理商： | MC68SZ328 |
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MC9328MX1 Advance Information, Rev. 4
88
Freescale Semiconductor
Specifications
3.22 CMOS Sensor Interface
The CSI module consists of a control register to configure the interface timing, a control register for statistic data
generation, a status register, interface logic, a 32
×
32 image data receive FIFO, and a 16
×
32 statistic data FIFO.
3.22.1 Gated Clock Mode
Figure 68 shows the timing diagram when the CMOS sensor output data is configured for negative edge and the
CSI is programmed to received data on the positive edge. Figure 69 on page 89 shows the timing diagram when the
CMOS sensor output data is configured for positive edge and the CSI is programmed to received data in negative
edge. The parameters for the timing diagrams are listed in Table 42 on page 89.
28
STCK high to STXD high impedance
17.90
29.75
15.7
26.1
ns
29
SRXD setup time before SRCK low
1.14
–
1.0
–
ns
30
SRXD hole time after SRCK low
0
–
0
–
ns
Synchronous Internal Clock Operation (Port B Alternate Function)
2
31
SRXD setup before STCK falling
18.81
–
16.5
–
ns
32
SRXD hold after STCK falling
0
–
0
–
ns
Synchronous External Clock Operation (Port B Alternate Function)
2
33
SRXD setup before STCK falling
1.14
–
1.0
–
ns
34
SRXD hold after STCK falling
0
–
0
–
ns
1.
All the timings for both SSI modules are given for a non-inverted serial clock polarity (TSCKP/RSCKP =
0) and a non-inverted frame sync (TFSI/RFSI = 0). If the polarity of the clock and/or the frame sync have
been inverted, all the timing remains valid by inverting the clock signal STCK/SRCK and/or the frame sync
STFS/SRFS shown in the tables and in the figures.
There is one set of I/O signals for the SSI2 module. They are from Port C alternate function (PC19 –
PC24). When SSI signals are configured as outputs, they can be viewed at Port C alternate function a.
When SSI signals are configured as inputs, the SSI module selects the input based on FMCR register bits
in the Clock controller module (CRM). By default, the input is selected from Port C alternate function.
bl = bit length; wl = word length
2.
3.
Table 41. SSI 2 Timing Parameter Table (Continued)
Ref
No.
Parameter
1.8V +/- 0.10V
3.0V +/- 0.30V
Unit
Minimum
Maximum
Minimum
Maximum
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|---|---|
| MC68SZ328ACVM66 | 功能描述:IC MPU DRAGONBALL SZ 196-PBGA RoHS:是 類別:集成電路 (IC) >> 嵌入式 - 微處理器 系列:M683xx 標(biāo)準(zhǔn)包裝:1 系列:MPC85xx 處理器類型:32-位 MPC85xx PowerQUICC III 特點:- 速度:1.2GHz 電壓:1.1V 安裝類型:表面貼裝 封裝/外殼:783-BBGA，F(xiàn)CBGA 供應(yīng)商設(shè)備封裝:783-FCPBGA（29x29） 包裝:托盤 |
| MC68SZ328ACVMR2 | 功能描述:IC MPU DRAGONBALL SZ 196-PBGA RoHS:是 類別:集成電路 (IC) >> 嵌入式 - 微處理器 系列:M683xx 標(biāo)準(zhǔn)包裝:1 系列:MPC85xx 處理器類型:32-位 MPC85xx PowerQUICC III 特點:- 速度:1.2GHz 電壓:1.1V 安裝類型:表面貼裝 封裝/外殼:783-BBGA，F(xiàn)CBGA 供應(yīng)商設(shè)備封裝:783-FCPBGA（29x29） 包裝:托盤 |
| MC68SZ328AVH66 | 制造商:Freescale Semiconductor 功能描述:Microprocessor IC Processor Ty |
| MC68SZ328AVM66 | 功能描述:IC MPU DRAGONBALL SZ 196-PBGA RoHS:是 類別:集成電路 (IC) >> 嵌入式 - 微處理器 系列:M683xx 標(biāo)準(zhǔn)包裝:1 系列:MPC85xx 處理器類型:32-位 MPC85xx PowerQUICC III 特點:- 速度:1.2GHz 電壓:1.1V 安裝類型:表面貼裝 封裝/外殼:783-BBGA，F(xiàn)CBGA 供應(yīng)商設(shè)備封裝:783-FCPBGA（29x29） 包裝:托盤 |
| MC68SZ328VH66V | 制造商:Freescale Semiconductor 功能描述: |
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