參數(shù)資料
型號: MC705JP7CPE
廠商: Freescale Semiconductor
文件頁數(shù): 3/164頁
文件大?。?/td> 0K
描述: IC MCU 8BIT 224 BYTES RAM 28PDIP
標準包裝: 13
系列: HC05
核心處理器: HC05
芯體尺寸: 8-位
速度: 2.1MHz
連通性: SIO
外圍設備: POR,溫度傳感器,WDT
輸入/輸出數(shù): 22
程序存儲器容量: 6KB(6K x 8)
程序存儲器類型: OTP
RAM 容量: 224 x 8
電壓 - 電源 (Vcc/Vdd): 2.7 V ~ 5.5 V
數(shù)據(jù)轉換器: A/D 4x12b
振蕩器型: 內(nèi)部
工作溫度: -40°C ~ 85°C
封裝/外殼: 28-DIP(0.600",15.24mm)
包裝: 管件
Simple Synchronous Serial Interface
MC68HC705JJ7 MC68HC705JP7 Advance Information Data Sheet, Rev. 4.1
100
Freescale Semiconductor
9.3.3 SIOP Data Register
The SIOP data register (SDR) is located at address $000C and serves as both the transmit and receive
data register. Writing to this register will initiate a message transmission if the node is in master mode.
The SIOP subsystem is not double buffered and any write to this register will destroy the previous
contents. The SDR can be read at any time. However, if a transfer is in progress the results may be
ambiguous. Writing to the SDR while a transfer is in progress can cause invalid data to be transmitted
and/or received. Figure 9-6 shows the position of each bit in the register. This register is not affected by
reset.
Address:
$000C
Bit 7
654321
Bit 0
Read:
Bit 7
654321
Bit 0
Write:
Reset:
Unaffected by reset
Figure 9-6. SIOP Data Register (SDR)
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