參數(shù)資料
型號： MC705JP7CPE
廠商： Freescale Semiconductor
文件頁數(shù)： 7/164頁
文件大?。?/td> 0K
描述： IC MCU 8BIT 224 BYTES RAM 28PDIP
標準包裝： 13
系列： HC05
核心處理器： HC05
芯體尺寸： 8-位
速度： 2.1MHz
連通性： SIO
外圍設(shè)備： POR，溫度傳感器，WDT
輸入/輸出數(shù)： 22
程序存儲器容量： 6KB（6K x 8）
程序存儲器類型： OTP
RAM 容量： 224 x 8
電壓 - 電源 (Vcc/Vdd)： 2.7 V ~ 5.5 V
數(shù)據(jù)轉(zhuǎn)換器： A/D 4x12b
振蕩器型： 內(nèi)部
工作溫度： -40°C ~ 85°C
封裝/外殼： 28-DIP（0.600"，15.24mm）
包裝： 管件
Core Timer
MC68HC705JJ7 MC68HC705JP7 Advance Information Data Sheet, Rev. 4.1
104
Freescale Semiconductor
periodically by a program sequence. Writing a logic 0 to COPC bit in the COPR register clears the COP
watchdog and prevents a COP reset.
EPMSEC — EPROM Security((1)) Bit
The EPMSEC bit is a write-only security bit to protect the contents of the user EPROM code stored in
locations $0700–$1FFF.
OPT — Optional Features Bit
The OPT bit enables two additional features: direct drive by comparator outputs to port A and voltage
offset capability to sample capacitor in analog subsystem.
1 = Optional features enabled
0 = Optional features disabled
COPC — COP Clear Bit
This write-only bit resets the COP watchdog. The COP watchdog is active in the run, wait, and halt
modes of operation if the COP is enabled by setting the COPEN bit in the MOR. The STOP instruction
disables the COP watchdog by clearing the counter and turning off its clock source.
In applications that depend on the COP watchdog, the STOP instruction can be disabled by setting the
SWAIT bit in the MOR. In applications that have wait cycles longer than the COP timeout period, the
COP watchdog can be disabled by clearing the COPEN bit. Table 10-2 summarizes recommended
conditions for enabling and disabling the COP watchdog.
NOTE
If the voltage on the IRQ/VPP pin exceeds 1.5 × VDD, the COP watchdog
turns off and remains off until the IRQ/VPP pin voltage falls below
1.5
× VDD.
Address:
$1FF0
Bit 7
6
5
4321
Bit 0
Read:
OPT
Write:
EPMSEC
COPC
Reset:
Unaffected by reset
= Unimplemented
Figure 10-4. COP and Security Register (COPR)
1. No security feature is absolutely secure. However, Freescale’s strategy is to make reading or copying the EPROM/OTPROM
difficult for unauthorized users.
Table 10-2. COP Watchdog Recommendations
Voltage on
IRQ/VPP Pin
SWAIT
(in MOR)(1)
1. The SWAIT bit in the MOR converts STOP instructions to HALT instructions.
Wait/Halt Time
Recommended COP
Watchdog Condition
Less than 1.5
× VDD
1
Less than COP
timeout period
Enabled(2)
2. Reset the COP watchdog immediately before executing the WAIT/HALT instruction.
Less than 1.5
× VDD
1
Greater than COP
timeout period
Disabled
Less than 1.5
× VDD
0
X(3)
3. Don’t care
Disabled
More than 1.5
× VDD
X
X(3)
Disabled
相關(guān)PDF資料
PDF描述
S912XEG128J2MAA MCU 16BIT 128K FLASH 16K 80QFP
MC9S12XD64MAA IC MCU 16BIT 64K FLASH 80-QFP
MC56F8322VFAER2 IC HYBRID CTRLR 16BIT 48-LQFP
MCF5207CVM166J IC MCU 32BIT RISC 144-MAPBGA
MC68908GZ16MFJE IC MCU 8BIT 16K FLASH 32-LQFP
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
MC705JP7CPE 制造商:Freescale Semiconductor 功能描述:IC 8BIT MCU 68HC05 2.1MHZ DIP-28
MC705K1CP 制造商:Motorola Inc 功能描述:16 PIN DIP INTEGRATED CIRCUIT
MC705L16CFUE 功能描述:8位微控制器 -MCU 8B MCU W/ EPROM RoHS:否 制造商:Silicon Labs 核心:8051 處理器系列:C8051F39x 數(shù)據(jù)總線寬度:8 bit 最大時鐘頻率:50 MHz 程序存儲器大小:16 KB 數(shù)據(jù) RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:1.8 V to 3.6 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:QFN-20 安裝風格:SMD/SMT
MC705P6ACDWE 功能描述:8位微控制器 -MCU MCU 176 BYTES RAM A/D RoHS:否 制造商:Silicon Labs 核心:8051 處理器系列:C8051F39x 數(shù)據(jù)總線寬度:8 bit 最大時鐘頻率:50 MHz 程序存儲器大小:16 KB 數(shù)據(jù) RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:1.8 V to 3.6 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:QFN-20 安裝風格:SMD/SMT
MC705P6ACDWE 制造商:Freescale Semiconductor 功能描述:8-Bit Microcontroller IC
發(fā)布緊急采購，3分鐘左右您將得到回復。

采購需求

(若只采購一條型號，填寫一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進入我的后臺，查看報價

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進入我的后臺，查看報價

*型號 *數(shù)量 廠商 批號 封裝
添加更多采購

我的聯(lián)系方式

*
*
*