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參數(shù)資料
| 型號： | MC7445ARX1000LG |
| 廠商： | 飛思卡爾半導(dǎo)體(中國)有限公司 |
| 英文描述： | RISC Microprocessor Hardware Specifications |
| 中文描述： | RISC微處理器硬件規(guī)格 |
| 文件頁數(shù)： | 26/64頁 |
| 文件大?。?/td> | 1127K |
| 代理商： | MC7445ARX1000LG |
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MPC7455 RISC Microprocessor Hardware Specifications, Rev. 4.1
26
Freescale Semiconductor
Electrical and Thermal Characteristics
Figure 10
shows the L3 bus timing diagrams for the MPC7455 interfaced to MSUG2 SRAMs.
Figure 10. L3 Bus Timing Diagrams for L3 Cache DDR SRAMs
5.2.4.2 L3 Bus AC Specifications for PB2 and Late Write SRAMs
When using PB2 or late write SRAMs at the L3 interface, the parts should be connected as shown in
Figure 11
.
These SRAMs are synchronous to the MPC7455; one L3_CLK
n
signal is output to each SRAM to latch address,
control, and write data. Read data is launched by the SRAM synchronous to the delayed L3_CLK
n
signal it received.
The MPC7455 needs a copy of that delayed clock which launched the SRAM read data to know when the returning
data will be valid. Therefore, L3_ECHO_CLK1 and L3_ECHO_CLK3 must be routed halfway to the SRAMs and
then returned to the MPC7455 inputs L3_ECHO_CLK0 and L3_ECHO_CLK2, respectively. Thus,
L3_ECHO_CLK0 and L3_ECHO_CLK2 are phase-aligned with the input clock received at the SRAMs. The
MPC7455 will latch the incoming data on the rising edge of L3_ECHO_CLK0 and L3_ECHO_CLK2.
L3_ECHO_CLK[0,1,2,3]
L3 Data and Data
Parity Inputs
VM
VM = Midpoint Voltage (GV
DD
/2)
L3_CLK[0,1]
ADDR, L3CNTL
VM
t
L3CHOV
t
L3CHOX
VM
L3DATA WRITE
t
L3CHOZ
VM
VM
VM
VM
t
L3CHDV
t
L3CHDX
VM
VM
VM
Outputs
Inputs
t
L3CLDV
t
L3CLDX
t
L3CLDZ
t
L3DVEH
t
L3DXEL
t
L3DVEL
t
L3DXEH
Note:
t
L3DVEH
and t
L3DVEL
as drawn here will be negative numbers, that is, input setup time will be
time after the clock edge.
Note:
t
L3CHDV
and t
L3CLDV
as drawn here will be negative numbers, that is, output valid time will be
time before the clock edge.
VM = Midpoint Voltage (GV
DD
/2)
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