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參數(shù)資料
| 型號： | MC7445ARX1000LG |
| 廠商： | 飛思卡爾半導體(中國)有限公司 |
| 英文描述： | RISC Microprocessor Hardware Specifications |
| 中文描述： | RISC微處理器硬件規(guī)格 |
| 文件頁數(shù)： | 7/64頁 |
| 文件大?。?/td> | 1127K |
| 代理商： | MC7445ARX1000LG |
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MPC7455 RISC Microprocessor Hardware Specifications, Rev. 4.1
Freescale Semiconductor
7
Comparison with the MPC7400, MPC7410, MPC7450, MPC7451, and MPC7441
Performance monitor can be used to help debug system designs and improve software efficiency
In-system testability and debugging features through JTAG boundary-scan capability
Testability
— LSSD scan design
— IEEE 1149.1 JTAG interface
— Array built-in self test (ABIST)—factory test only
Reliability and serviceability
— Parity checking on system bus and L3 cache bus
— Parity checking on the L2 and L3 cache tag arrays
3
Comparison with the MPC7400, MPC7410, MPC7450,
MPC7451, and MPC7441
Table 1
compares the key features of the MPC7455 with the key features of the earlier MPC7400, MPC7410,
MPC7450, MPC7451, and MPC7441. To achieve a higher frequency, the number of logic levels per cycle is
reduced. Also, to achieve this higher frequency, the pipeline of the MPC7455 is extended (compared to the
MPC7400), while maintaining the same level of performance as measured by the number of instructions executed
per cycle (IPC).
Table 1. Microarchitecture Comparison
Microarchitectural Specs
MPC7455/MPC7445
MPC7450/MPC7451/
MPC7441
MPC7400/MPC7410
Basic Pipeline Functions
Logic inversions per cycle
18
18
28
Pipeline stages up to execute
5
5
3
Total pipeline stages (minimum)
7
7
4
Pipeline maximum instruction
throughput
3 + Branch
3 + Branch
2 + Branch
Pipeline Resources
Instruction buffer size
12
12
6
Completion buffer size
16
16
8
Renames (integer, float, vector)
16, 16, 16
16, 16, 16
6, 6, 6
Maximum Execution Throughput
SFX
3
3
2
Vector
2 (Any 2 of 4 Units)
2 (Any 2 of 4 Units)
2 (Permute/Fixed)
Scalar floating-point
1
1
1
Out-of-Order Window Size in Execution Queues
SFX integer units
1 Entry
×
3 Queues
1 Entry
×
3 Queues
1 Entry
×
2 Queues
Vector units
In Order, 4 Queues
In Order, 4 Queues
In Order, 2 Queues
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