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參數(shù)資料
| 型號： | MC74HC589ADR2 |
| 廠商： | ON Semiconductor |
| 文件頁數(shù)： | 13/14頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC SHIFT REGISTR 8BIT 3ST 16SOIC |
| 產品變化通告： | Product Discontinuation 27/Jan/2012 |
| 標準包裝： | 1 |
| 系列： | 74HC |
| 邏輯類型： | 移位寄存器 |
| 輸出類型： | 標準 |
| 元件數(shù)： | 1 |
| 每個元件的位元數(shù)： | 8 |
| 功能： | 通用 |
| 電源電壓： | 2 V ~ 6 V |
| 工作溫度： | -55°C ~ 125°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 16-SOIC（0.154"，3.90mm 寬） |
| 供應商設備封裝： | 16-SOIC |
| 包裝： | 剪切帶 (CT) |
| 其它名稱： | MC74HC589ADR2OSCT |
MC74HC589A
http://onsemi.com
8
AH
50%
LATCH
CLOCK
VCC
GND
*Includes all probe and jig capacitance.
CL*
TEST POINT
DEVICE
UNDER
TEST
OUTPUT
DATA
VALID
tsu
th
SA
50%
SHIFT
CLOCK
VCC
GND
tsu
th
SERIAL SHIFT/
PARALLEL
LOAD
50%
SHIFT
CLOCK
VCC
GND
tsu
Figure 7.
Figure 8.
Figure 9.
Figure 10. Test Circuit
Switching Waveforms
Figure 11. Test Circuit
*Includes all probe and jig capacitance.
CL*
TEST POINT
DEVICE
UNDER
TEST
OUTPUT
CONNECT TO VCC WHEN
TESTING tPLZ AND tPZL.
CONNECT TO GND WHEN
TESTING tPHZ AND tPZH.
1 kW
DATA
VALID
Pin Descriptions
Data Inputs
A, B, C, D, E, F, G, H (Pins 15, 1, 2, 3, 4, 5, 6, 7)
Parallel data inputs. Data on these inputs are stored in the
data latch on the rising edge of the Latch Clock input.
SA (Pin 14)
Serial data input. Data on this input is shifted into the shift
register on the rising edge of the Shift Clock input if Serial
Shift/Parallel Load is high. Data on this input is ignored
when Serial Shift/Parallel Load is low.
Control Inputs
Serial Shift/Parallel Load (Pin 13)
Shift register mode control. When a high level is applied
to this pin, the shift register is allowed to serially shift data.
When a low level is applied to this pin, the shift register
accepts parallel data from the data latch.
Shift Clock (Pin 11)
Serial shift clock. A lowtohigh transition on this input
shifts data on the serial data input into the shift register and
data in stage H is shifted out QH, being replaced by the data
previously stored in stage G.
Latch Clock (Pin 12)
Data latch clock. A lowtohigh transition on this input
loads the parallel data on inputs AH into the data latch.
Output Enable (Pin 10)
Activelow output enable A high level applied to this pin
forces the QH output into the high impedance state. A low
level enables the output. This control does not affect the state
of the input latch or the shift register.
Output
QH (Pin 9)
Serial data output. This pin is the output from the last stage
of the shift register. This is a 3state output.
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| MC74HC589ADR2G | 功能描述:計數(shù)器移位寄存器 8-Bit 3 State Shift RoHS:否 制造商:Texas Instruments 計數(shù)器類型: 計數(shù)順序:Serial to Serial/Parallel 電路數(shù)量:1 封裝 / 箱體:SOIC-20 Wide 邏輯系列: 邏輯類型: 輸入線路數(shù)量:1 輸出類型:Open Drain 傳播延遲時間:650 ns 最大工作溫度:+ 125 C 最小工作溫度:- 40 C 封裝:Reel |
| MC74HC589ADT | 制造商:Rochester Electronics LLC 功能描述:- Tape and Reel |
| MC74HC589ADTR2 | 功能描述:計數(shù)器移位寄存器 8-Bit 3 State Shift RoHS:否 制造商:Texas Instruments 計數(shù)器類型: 計數(shù)順序:Serial to Serial/Parallel 電路數(shù)量:1 封裝 / 箱體:SOIC-20 Wide 邏輯系列: 邏輯類型: 輸入線路數(shù)量:1 輸出類型:Open Drain 傳播延遲時間:650 ns 最大工作溫度:+ 125 C 最小工作溫度:- 40 C 封裝:Reel |
| MC74HC589ADTR2G | 功能描述:計數(shù)器移位寄存器 8-Bit 3 State Shift RoHS:否 制造商:Texas Instruments 計數(shù)器類型: 計數(shù)順序:Serial to Serial/Parallel 電路數(shù)量:1 封裝 / 箱體:SOIC-20 Wide 邏輯系列: 邏輯類型: 輸入線路數(shù)量:1 輸出類型:Open Drain 傳播延遲時間:650 ns 最大工作溫度:+ 125 C 最小工作溫度:- 40 C 封裝:Reel |
| MC74HC589ADTR2G-CUT TAPE | 制造商:ON 功能描述:MC74HC589A Series 2 to 6 V CMOS 8-Bit Shift Register - TSSOP-16 |
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