AC ELECTRICAL CHARACTERISTICS (CL
參數(shù)資料
型號: MC74HCT595ADG
廠商: ON Semiconductor
文件頁數(shù): 7/11頁
文件大小: 0K
描述: IC SHIFT REGISTER 8BIT 16SOIC
標(biāo)準(zhǔn)包裝: 48
系列: 74HCT
邏輯類型: 移位寄存器
輸出類型: 三態(tài)
元件數(shù): 1
每個元件的位元數(shù): 8
功能: 串行至并行
電源電壓: 4.5 V ~ 5.5 V
工作溫度: -55°C ~ 125°C
安裝類型: 表面貼裝
封裝/外殼: 16-SOIC(0.154",3.90mm 寬)
供應(yīng)商設(shè)備封裝: 16-SOIC
包裝: 管件
MC74HCT595A
http://onsemi.com
5
AC ELECTRICAL CHARACTERISTICS (CL = 50 pF, Input tr = tf = 6.0 ns)
Symbol
Parameter
VCC
V
Guaranteed Limit
Unit
– 55 to 25_C
v 85_C
v 125_C
fmax
Maximum Clock Frequency (50% Duty Cycle)
(Figures 1 and 7)
4.5 to
5.5
30
24
20
MHz
tPLH,
tPHL
Maximum Propagation Delay, Shift Clock to SQH
(Figures 1 and 7)
4.5 to
5.5
28
35
42
ns
tPHL
Maximum Propagation Delay, Reset to SQH
(Figures 2 and 7)
4.5 to
5.5
29
36
44
ns
tPLH,
tPHL
Maximum Propagation Delay, Latch Clock to QA QH
(Figures 3 and 7)
4.5 to
5.5
28
35
42
ns
tPLZ,
tPHZ
Maximum Propagation Delay, Output Enable to QA QH
(Figures 4 and 8)
4.5 to
5.5
30
38
45
ns
tPZL,
tPZH
Maximum Propagation Delay, Output Enable to QA QH
(Figures 4 and 8)
4.5 to
5.5
27
34
41
ns
tTLH,
tTHL
Maximum Output Transition Time, QA QH
(Figures 3 and 7)
4.5 to
5.5
12
15
18
ns
tTLH,
tTHL
Maximum Output Transition Time, SQH
(Figures 1 and 7)
4.5 to
5.5
15
19
22
ns
Cin
Maximum Input Capacitance
10
pF
Cout
Maximum ThreeState Output Capacitance (Output in
HighImpedance State), QA QH
15
pF
CPD
Power Dissipation Capacitance (Per Package)*
Typical @ 25°C, VCC = 5.0 V
pF
300
* Used to determine the noload dynamic power consumption: PD = CPD VCC2f + ICC VCC.
TIMING REQUIREMENTS (Input tr = tf = 6.0 ns)
Symbol
Parameter
VCC
V
Guaranteed Limit
Unit
25_C to –55_C
v 85_C
v 125_C
tsu
Minimum Setup Time, Serial Data Input A to Shift Clock
(Figure 5)
4.5 to
5.5
10
13
15
ns
tsu
Minimum Setup Time, Shift Clock to Latch Clock
(Figure 6)
4.5 to
5.5
15
19
22
ns
th
Minimum Hold Time, Shift Clock to Serial Data Input A
(Figure 5)
4.5 to
5.5
5.0
5.0
5.0
ns
trec
Minimum Recovery Time, Reset Inactive to Shift Clock
(Figure 2)
4.5 to
5.5
10
13
15
ns
tw
Minimum Pulse Width, Reset
(Figure 2)
4.5 to
5.5
12
15
18
ns
tw
Minimum Pulse Width, Shift Clock
(Figure 1)
4.5 to
5.5
10
13
15
ns
tw
Minimum Pulse Width, Latch Clock
(Figure 6)
4.5 to
5.5
10
13
15
ns
tr, tf
Maximum Input Rise and Fall Times
(Figure 1)
4.5 to
5.5
500
500
500
ns
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