49
8023F–AVR–07/09
ATmega325P/3250P
ADC is used. To reduce power consumption in Power-down mode, the user can avoid the three
conditions above to ensure that the reference is turned off before entering Power-down mode.
10.4
Watchdog Timer
The Watchdog Timer is clocked from a separate On-chip Oscillator which runs at 1 MHz. This is
the typical value at V
CC = 5V. See characterization data for typical values at other VCC levels. By
controlling the Watchdog Timer prescaler, the Watchdog Reset interval can be adjusted as
dog Timer. The Watchdog Timer is also reset when it is disabled and when a Chip Reset occurs.
Eight different clock cycle periods can be selected to determine the reset period. If the reset
period expires without another Watchdog Reset, the ATmega325P/3250P resets and executes
from the Reset Vector. For timing details on the Watchdog Reset, refer to
Table 10-2 on pageTo prevent unintentional disabling of the Watchdog or unintentional change of time-out period,
two different safety levels are selected by the fuse WDTON as shown in
Figure 10-1 Refer to
details.
Figure 10-7. Watchdog Timer
10.4.1
Timed Sequences for Changing the Configuration of the Watchdog Timer
The sequence for changing configuration differs slightly between the two safety levels. Separate
procedures are described for each level.
10.4.2
Safety Level 1
In this mode, the Watchdog Timer is initially disabled, but can be enabled by writing the WDE bit
to 1 without any restriction. A timed sequence is needed when changing the Watchdog Time-out
period or disabling an enabled Watchdog Timer. To disable an enabled Watchdog Timer, and/or
changing the Watchdog Time-out, the following procedure must be followed:
Table 10-1.
WDT Configuration as a Function of the Fuse Settings of WDTON
WDTON
Safety
Level
WDT Initial
State
How to Disable the
WDT
How to Change Time-
out
Unprogrammed
1
Disabled
Timed sequence
Programmed
2
Enabled
Always enabled
Timed sequence
WATCHDOG
OSCILLATOR