150
8023F–AVR–07/09
ATmega325P/3250P
Bit 5:4 – COM2A1:0: Compare Match Output Mode A
These bits control the Output Compare pin (OC2A) behavior. If one or both of the COM2A1:0
bits are set, the OC2A output overrides the normal port functionality of the I/O pin it is connected
to. However, note that the Data Direction Register (DDR) bit corresponding to OC2A pin must be
set in order to enable the output driver.
When OC2A is connected to the pin, the function of the COM2A1:0 bits depends on the
WGM21:0 bit setting.
Table 16-3 shows the COM2A1:0 bit functionality when the WGM21:0 bits
are set to a normal or CTC mode (non-PWM).
Table 16-4 shows the COM2A1:0 bit functionality when the WGM21:0 bits are set to fast PWM
mode.
Note:
1. A special case occurs when OCR2A equals TOP and COM2A1 is set. In this case, the com-
for more details.
Table 16-5 shows the COM21:0 bit functionality when the WGM21:0 bits are set to phase cor-
rect PWM mode.
Note:
1. A special case occurs when OCR2A equals TOP and COM2A1 is set. In this case, the com-
Table 16-3.
Compare Output Mode, non-PWM Mode
COM2A1
COM2A0
Description
0
Normal port operation, OC2A disconnected.
0
1
Toggle OC2A on compare match.
1
0
Clear OC2A on compare match.
1
Set OC2A on compare match.
Table 16-4.
Compare Output Mode, Fast PWM M
odeCOM2A1
COM2A0
Description
0
Normal port operation, OC2A disconnected.
01
Reserved
10
Clear OC2A on compare match, set OC2A at BOTTOM,
(non-inverting mode)
11
Set OC2A on compare match, clear OC2A at BOTTOM,
(inverting mode)
Table 16-5.
Compare Output Mode, Phase Correct PWM Mode
COM2A1
COM2A0
Description
0
Normal port operation, OC2A disconnected.
01
Reserved
10
Clear OC2A on compare match when up-counting. Set OC2A on
compare match when counting down.
11
Set OC2A on compare match when up-counting. Clear OC2A on
compare match when counting down.