參數(shù)資料
型號: MC80C52XXX-16SHXXX:D
廠商: TEMIC SEMICONDUCTORS
元件分類: 微控制器/微處理器
英文描述: 8-BIT, MROM, 16 MHz, MICROCONTROLLER, CDIP40
文件頁數(shù): 67/141頁
文件大小: 7628K
245
32117D–AVR-01/12
AT32UC3C
14.7.14
Overrun Status Register
Name:
OVSR0 - OVSR1
Access Type:
Read-only
Offset:
0x0B0 - 0x0B4
Reset Value:
0x00000000
OVS: Overrun Interrupt Status
0: An interrupt event has not occurred
1: An interrupt event has occurred
This bit is cleared by writing a one to the corresponding bit in OVSCR.
Note:
Channels 0 to 31 are controlled by OVSR0.
Channels 32 to 63 are controlled by OVSR1.
Please refer to the Module Configuration section at the end of this Chapter for device-specific channel mapping information.
31
30
29
28
27
26
25
24
OVS
23
22
21
20
19
18
17
16
OVS
15
14
13
12
11
10
9
8
OVS
76
543
21
0
OVS
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