參數(shù)資料
型號: MC8641HX1000GE
廠商: Freescale Semiconductor
文件頁數(shù): 11/130頁
文件大?。?/td> 0K
描述: IC DUAL CORE PROCESSOR 994-CBGA
標準包裝: 1
系列: MPC86xx
處理器類型: 32-位 MPC86xx PowerPC
速度: 1.0GHz
電壓: 1.05V
安裝類型: 表面貼裝
封裝/外殼: 994-BCBGA,F(xiàn)CCBGA
供應(yīng)商設(shè)備封裝: 994-FCCBGA(33x33)
包裝: 托盤
MPC8641 and MPC8641D Integrated Host Processor Hardware Specifications, Rev. 2
108
Freescale Semiconductor
Clocking
18.4.1
SYSCLK to Platform Frequency Options
Table 70 shows some SYSCLK frequencies and the expected MPX frequency values based on the MPX
clock to SYSCLK ratio. Note that frequencies between 400 MHz and 500 MHz are NOT supported on the
platform. See note regarding cfg_platform_freq in Section 17, “Signal Listings,” because it is a reset
configuration pin that is related to platform frequency.
18.4.2
Platform to FIFO Restrictions
Please note the following FIFO maximum speed restrictions based on platform speed.
For FIFO GMII mode:
FIFO TX/RX clock frequency <= platform clock frequency/4.2
For example, if the platform frequency is 533 MHz, the FIFO TX/RX clock frequency should be no more
than 127 MHz
For FIFO encoded mode:
FIFO TX/RX clock frequency <= platform clock frequency/3.2
For example, if the platform frequency is 533 MHz, the FIFO TX/RX clock frequency should be no more
than 167 MHz
Table 70. Frequency Options of SYSCLK with Respect to Platform/MPX Clock Speed
MPX to
SYSCLK
Ratio
SYSCLK (MHz)
66
83
100
111
133
167
Platform/MPX Frequency (MHz)1
1 SYSCLK frequency range is 66-167 MHz. Platform clock/ MPX frequency
range is 400 MHz, 500-600 MHz.
2
3
400
500
4
400
533
5
500
555
6
400
500
600
8
533
9
600
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