參數(shù)資料
型號： MC8641HX1000GE
廠商： Freescale Semiconductor
文件頁數(shù)： 35/130頁
文件大?。?/td> 0K
描述： IC DUAL CORE PROCESSOR 994-CBGA
標準包裝： 1
系列： MPC86xx
處理器類型： 32-位 MPC86xx PowerPC
速度： 1.0GHz
電壓： 1.05V
安裝類型： 表面貼裝
封裝/外殼： 994-BCBGA，F(xiàn)CCBGA
供應(yīng)商設(shè)備封裝： 994-FCCBGA（33x33）
包裝： 托盤
MPC8641 and MPC8641D Integrated Host Processor Hardware Specifications, Rev. 2
Freescale Semiconductor
13
Electrical Characteristics
Figure 3 illustrates the Power Up sequence as described above.
Figure 3. MPC8641 Power-Up and Reset Sequence
VDD_PLAT, AVDD_PLAT
L/T/OVDD
Time
2.5 V
3.3 V
1.2 V
0
DC
P
o
wer
Su
ppl
y
V
o
lt
age
Reset
Configuration Pins
HRESET (& TRST)
100 s Platform PLL
Asserted for
100
μs after
Power Supply Ramp Up 2
Notes:
1. Dotted waveforms correspond to optional supply values for a specified power supply. See Table 2.
2. The recommended maximum ramp up time for power supplies is 20 milliseconds.
3. Refer to Section 5, “RESET Initialization” for additional information on PLL relock and reset signal
assertion timing requirements.
4. Refer to Table 11 for additional information on reset configuration pin setup timing requirements. In
addition see Figure 68 regarding HRESET and JTAG connection details including TRST.
5. e600 PLL relock time is 100 microseconds maximum plus 255 MPX_clk cycles.
6. Stable PLL configuration signals are required as stable SYSCLK is applied. All other POR configuration
inputs are required 4 SYSCLK cycles before HRESET negation and are valid at least 2 SYSCLK cycles
after HRESET has negated (hold requirement). See Section 5, “RESET Initialization” for more
information on setup and hold time of reset configuration signals.
7. VDD_PLAT, AVDD_PLAT must strictly reach 90% of their recommended voltage before the rail for
D
n_GVDD, and Dn_MVREF reaches 10% of their recommended voltage.
8. SYSCLK must be driven only AFTER the power for the various power supplies is stable.
9. In device sleep mode, the reset configuration signals for DRAM types (TSEC2_TXD[4],TSEC2_TX_ER)
must be valid BEFORE HRESET is asserted.
e6005
AVDD_LB, SVDD, XVDD_SRDSn
VDD_Coren, AVDD_Coren
AVDD_SRDSn
1.8 V
D
n_GVDD, = 1.8/2.5 V
D
n_MVREF
If
SYSCLK 8 (not drawn to scale)
Relock Time 3
L/TVDD=2.5 V
1
7
PLL
9
SYSCLK is functional 4
Cycles Setup and hold Time 6
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MC8641HX1000H 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:Integrated Host Processor Hardware Specifications
MC8641HX1000J 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:Integrated Host Processor Hardware Specifications
MC8641HX1000K 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:Integrated Host Processor Hardware Specifications
MC8641HX1000N 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:Integrated Host Processor Hardware Specifications
MC8641HX1000NB 功能描述:微處理器 - MPU G8 REV 2.0 0.95V 105C RoHS:否 制造商:Atmel 處理器系列:SAMA5D31 核心:ARM Cortex A5 數(shù)據(jù)總線寬度:32 bit 最大時鐘頻率:536 MHz 程序存儲器大小:32 KB 數(shù)據(jù) RAM 大小:128 KB 接口類型:CAN, Ethernet, LIN, SPI,TWI, UART, USB 工作電源電壓:1.8 V to 3.3 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-324
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