參數(shù)資料
型號(hào)： MC8641HX1000NE
廠商： Freescale Semiconductor
文件頁數(shù)： 112/130頁
文件大?。?/td> 0K
描述： IC DUAL CORE PROCESSOR 994-CBGA
標(biāo)準(zhǔn)包裝： 1
系列： MPC86xx
處理器類型： 32-位 MPC86xx PowerPC
速度： 1.0GHz
電壓： 0.95V
安裝類型： 表面貼裝
封裝/外殼： 994-BCBGA，F(xiàn)CCBGA
供應(yīng)商設(shè)備封裝： 994-FCCBGA（33x33）
包裝： 托盤
MPC8641 and MPC8641D Integrated Host Processor Hardware Specifications, Rev. 2
82
Freescale Semiconductor
Serial RapidIO
For each baud rate at which an LP-Serial transmitter is specified to operate, the output eye pattern of the
transmitter shall fall entirely within the unshaded portion of the Transmitter Output Compliance Mask
shown in Figure 54 with the parameters specified in Table 58 when measured at the output pins of the
device and the device is driving a 100
Ω +/–5% differential resistive load. The output eye pattern of an
LP-Serial transmitter that implements pre-emphasis (to equalize the link and reduce inter-symbol
interference) need only comply with the Transmitter Output Compliance Mask when pre-emphasis is
disabled or minimized.
Figure 54. Transmitter Output Compliance Mask
Table 57. Long Run Transmitter AC Timing Specifications—3.125 GBaud
Characteristic
Symbol
Range
Unit
Notes
Min
Max
Output Voltage,
VO
–0.40
2.30
Volts
Voltage relative to COMMON
of either signal comprising a
differential pair
Differential Output Voltage
VDIFFPP
800
1600
mV p-p
—
Deterministic Jitter
JD
—
0.17
UI p-p
—
Total Jitter
JT
—0.35
UI p-p
—
Multiple output skew
SMO
—
1000
ps
Skew at the transmitter output
between lanes of a multilane
link
Unit Interval
UI
320
ps
+/– 100 ppm
0
VDIFF min
VDIFF max
-VDIFF min
-VDIFF max
0B
1-B
1
Time in UI
T
ran
s
m
it
te
rDi
ff
e
re
n
ti
al
Out
put
V
o
lt
age
A1-A
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