參數(shù)資料
型號: MC88LV926DW
廠商: FREESCALE SEMICONDUCTOR INC
元件分類: 時鐘及定時
英文描述: 88LV SERIES, PLL BASED CLOCK DRIVER, 4 TRUE OUTPUT(S), 1 INVERTED OUTPUT(S), PDSO20
封裝: PLASTIC, SOIC-20
文件頁數(shù): 2/9頁
文件大?。?/td> 120K
代理商: MC88LV926DW
MC88LV926
54
FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA
Figure 1. Pinout: 20–Lead Wide SOIC Package (Top View)
Description of the RST_IN/RST_OUT(LOCK)
Functionality (continued)
After the system start–up is complete and the 88LV926 is
phase–locked to the SYNC input signal (RST_OUT high), the
processor reset functionality can be utilized. When the RST_IN
pin is toggled low (min. pulse width=10nS), RST_OUT(LOCK)
will go to the low state and remain there for 1024 cycles of the
‘Q' output frequency (512 SYNC cycles). During the time in
which the RST_OUT(LOCK) is actively pulled low, all the
88LV926 clock outputs will continue operating correctly and in a
locked condition to the SYNC input (clock signals to the
68030/040/060 family of processors must continue while the
processor is in reset). A propagation delay after the 1024th
cycle RST_OUT(LOCK) goes back to the high impedance state
to be pulled high by the resistor.
Power Supply Ramp Rate Restriction for Correct 030/040
Processor Reset Operation During System Start-up
Because the RST_OUT(LOCK) pin is an indicator of
phase-lock to the reference source, some constraints must be
placed on the power supply ramp rate to make sure the
RST_OUT(LOCK) signal holds the processor in reset during
system start-up (power–up). With the recommended loop filter
values (see Figure 7) the lock time is approximately 10ms. The
phase–lock loop will begin attempting to lock to a reference
source (if it is present) when VCC reaches 2V. If the VCC ramp
rate is significantly slower than 10ms, then the PLL could lock
to the reference source, causing RST_OUT(LOCK) to go high
before the 88LV926 and '030/040 processor is fully powered up,
violating the processor reset specification. Therefore, if it is
necessary for the RST_IN pin to be held high during power-up,
the VCC ramp rate must be less than 10mS for proper
68030/040/060 reset operation.
This ramp rate restriction can be ignored if the RST_IN pin
can be held low during system start-up (which holds RST_OUT
low). The RST_OUT(LOCK) pin will then be pulled back high
1024 cycles after the RST_IN pin goes high.
19
20
18
17
16
15
14
13
12
11
2
1
3
4
5
6
7
8
9
10
GND
Q3
2X_Q
VCC
QCLKEN
MR
VCC
RST_IN
Q2
VCC(AN)
GND
RC1
RST_OUT(LOCK)
GND(AN)
PLL_EN
SYNC
Q1
GND
VCC
Q0
Table 1. Capacitance and Power Specifications
Symbol
Parameter
Value Type
Unit
Test Conditions
CIN
Input Capacitance
4.51
1.
Value at VCC = 3.3 V TBD
pF
VCC = 5.0V
CPD
Power Dissipation Capacitance
401
pF
VCC = 5.0V
PD1
Power Dissipation at 33MHz With 50
Thevenin Termination
15mW/Output1
90mW/Device
mW
VCC = 5.0V
T = 25
°C
PD2
Power Dissipation at 33MHz With 50
Parallel Termination to GND
37.5mW/Output1
225mW/Device
mW
VCC = 5.0V
T = 25
°C
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