Slave LIN Interface Controller (SLIC) Module
MC68HC908QL4 MC68HC908QL3 MC68HC908QL2 Data Sheet, Rev. 4
144
Freescale Semiconductor
BT — Bit Time Value
BT displays the number of SLIC clocks that equals one bit time in LIN mode (BTM = 0). For details of
the use of the SLCBT registers in LIN mode for trimming of the internal oscillator, refer to
14.9.16
Oscillator Trimming with SLIC
.
BT sets the number of SLIC clocks that equals one bit time in byte transfer mode (BTM = 1). For details
of the use of the SLCBT registers in BTM mode, refer to
14.9.15 Byte Transfer Mode Operation
.
NOTE
Do not write to unimplemented bits as unexpected operation may occur.
14.8.6 SLIC State Vector Register
SLIC state vector register (SLCSV) is provided to substantially decrease the CPU overhead associated
with servicing interrupts while under operation of a LIN protocol. It provides an index offset that is directly
related to the LIN module’s current state, which can be used with a user supplied jump table to rapidly
enter an interrupt service routine. This eliminates the need for the user to maintain a duplicate state
machine in software.
READ: any time
WRITE: ignored
I[3:0] —
Interrupt State Vector (Bits 5–2)
These bits indicate the source of the interrupt request that is currently pending.
14.8.6.1 LIN Mode Operation
Table 14-2
shows the possible values for the possible sources for a SLIC interrupt while in LIN mode
operation (BTM = 0).
Bit 7
6
5
4
3
2
1
Bit 0
Read:
0
0
I3
I2
I1
I0
0
0
Write:
Reset:
0
0
0
0
0
0
0
0
= Unimplemented
Figure 14-10. SLIC State Vector Register (SLCSV)
Table 14-2. Interrupt Sources Summary (BTM = 0)
SLCSV
I3
I2
I1
I0
Interrupt Source
Priority
$00
0
0
0
0
No Interrupts Pending
0 (Lowest)
$04
0
0
0
1
No-Bus-Activity
1
$08
0
0
1
0
TX Message Buffer Empty
Checksum Transmitted
2
$0C
0
0
1
1
TX Message Buffer Empty
3
$10
0
1
0
0
RX Message Buffer Full
Checksum OK
4
$14
0
1
0
1
RX Data Buffer Full
No Errors
5
$18
0
1
1
0
Bit-Error
6