Chapter 22 DP512 Port Integration Module (S12XDP512PIMV2)
MC9S12XDP512 Data Sheet, Rev. 2.17
Freescale Semiconductor
831
22.3.2.7
Port C Data Direction Register (DDRC)
Read: Anytime. In emulation modes, read operations will return the data from the external bus, in all other
modes the data are read from this register.
Write: Anytime. In emulation modes, write operations will also be directed to the external bus.
22.3.2.8
Port D Data Direction Register (DDRD)
Read: Anytime. In emulation modes, read operations will return the data from the external bus, in all other
modes the data are read from this register.
Write: Anytime. In emulation modes, write operations will also be directed to the external bus.
76543210
R
DDRC7
DDRC6
DDRC5
DDRC4
DDRC3
DDRC2
DDRC1
DDRC0
W
Reset
00000000
Figure 22-9. Port C Data Direction Register (DDRC)
Table 22-10. DDRC Field Descriptions
Field
Description
7–0
DDRC[7:0]
Data Direction Port C — This register controls the data direction for port C. When Port C is operating as a general
purpose I/O port, DDRC determines whether each pin is an input or output. A logic level “1” causes the
associated port pin to be an output and a logic level “0” causes the associated pin to be a high-impedance input.
0 Associated pin is congured as input.
1 Associated pin is congured as output.
Note: Due to internal synchronization circuits, it can take up to 2 bus clock cycles until the correct value is read
on PORTC after changing the DDRC register.
76543210
R
DDRD7
DDRD6
DDRD5
DDRD4
DDRD3
DDRD2
DDRD1
DDRD0
W
Reset
00000000
Figure 22-10. Port D Data Direction Register (DDRD)
Table 22-11. DDRD Field Descriptions
Field
Description
7–0
DDRD[7:0]
Data Direction Port D — This register controls the data direction for port D. When Port D is operating as a general
purpose I/O port, DDRD determines whether each pin is an input or output. A logic level “1” causes the
associated port pin to be an output and a logic level “0” causes the associated pin to be a high-impedance input.
0 Associated pin is congured as input.
1 Associated pin is congured as output.
Note: Due to internal synchronization circuits, it can take up to 2 bus clock cycles until the correct value is read
on PORTD after changing the DDRD register.