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| 型號： | MC912XDP512J1CAGR |
| 廠商： | FREESCALE SEMICONDUCTOR INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 16-BIT, FLASH, 40 MHz, MICROCONTROLLER, PQFP144 |
| 封裝： | 20 X 20 MM, LEAD FREE, LQFP-144 |
| 文件頁數(shù)： | 727/1350頁 |
| 文件大小： | 7418K |
| 代理商： | MC912XDP512J1CAGR |
Chapter 10 Freescale’s Scalable Controller Area Network (S12MSCANV3)
MC9S12XDP512 Data Sheet, Rev. 2.17
Freescale Semiconductor
437
NOTE
The CANTBSEL register is held in the reset state when the initialization
mode is active (INITRQ = 1 and INITAK=1). This register is writable when
not in initialization mode (INITRQ = 0 and INITAK = 0).
Read: Find the lowest ordered bit set to 1, all other bits will be read as 0
Write: Anytime when not in initialization mode
The following gives a short programming example of the usage of the CANTBSEL register:
To get the next available transmit buffer, application software must read the CANTFLG register and write
this value back into the CANTBSEL register. In this example Tx buffers TX1 and TX2 are available. The
value read from CANTFLG is therefore 0b0000_0110. When writing this value back to CANTBSEL, the
Tx buffer TX1 is selected in the CANTXFG because the lowest numbered bit set to 1 is at bit position 1.
Reading back this value out of CANTBSEL results in 0b0000_0010, because only the lowest numbered
bit position set to 1 is presented. This mechanism eases the application software the selection of the next
available Tx buffer.
LDD CANTFLG; value read is 0b0000_0110
STD CANTBSEL; value written is 0b0000_0110
LDD CANTBSEL; value read is 0b0000_0010
If all transmit message buffers are deselected, no accesses are allowed to the CANTXFG registers.
10.3.2.12 MSCAN Identier Acceptance Control Register (CANIDAC)
The CANIDAC register is used for identier acceptance control as described below.
Table 10-15. CANTBSEL Register Field Descriptions
Field
Description
2:0
TX[2:0]
Transmit Buffer Select — The lowest numbered bit places the respective transmit buffer in the CANTXFG
register space (e.g., TX1 = 1 and TX0 = 1 selects transmit buffer TX0; TX1 = 1 and TX0 = 0 selects transmit
buffer TX1). Read and write accesses to the selected transmit buffer will be blocked, if the corresponding TXEx
bit is cleared and the buffer is scheduled for transmission (see Section 10.3.2.7, “MSCAN Transmitter Flag
0 The associated message buffer is deselected
1 The associated message buffer is selected, if lowest numbered bit
76543210
R0
0
IDAM1
IDAM0
0
IDHIT2
IDHIT1
IDHIT0
W
Reset:
00000000
= Unimplemented
Figure 10-15. MSCAN Identier Acceptance Control Register (CANIDAC)
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| MC912XDP512J1CALR | 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:HCS12X Microcontrollers |
| MC912XDP512J1CFUR | 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:HCS12X Microcontrollers |
| MC912XDP512J1CFVR | 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:HCS12X Microcontrollers |
| MC912XDP512J1CPVR | 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:HCS12X Microcontrollers |
| MC912XDP512J1MAAR | 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:HCS12X Microcontrollers |
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