Chapter 15 Background Debug Module (S12XBDMV2)
MC9S12XDP512 Data Sheet, Rev. 2.17
Freescale Semiconductor
575
6
BDMACT
BDM Active Status — This bit becomes set upon entering BDM. The standard BDM rmware lookup table is
then enabled and put into the memory map. BDMACT is cleared by a carefully timed store instruction in the
standard BDM rmware as part of the exit sequence to return to user code and remove the BDM memory from
the map.
1 BDM active
4
SDV
Shift Data Valid — This bit is set and cleared by the BDM hardware. It is set after data has been transmitted as
part of a rmware or hardware read command or after data has been received as part of a rmware or hardware
write command. It is cleared when the next BDM command has been received or BDM is exited. SDV is used
by the standard BDM rmware to control program ow execution.
0 Data phase of command not complete
1 Data phase of command is complete
3
TRACE
TRACE1 BDM Firmware Command is Being Executed — This bit gets set when a BDM TRACE1 rmware
command is rst recognized. It will stay set until BDM rmware is exited by one of the following BDM commands:
GO or GO_UNTIL.
0 TRACE1 command is not being executed
1 TRACE1 command is being executed
2
CLKSW
Clock Switch — The CLKSW bit controls which clock the BDM operates with. It is only writable from a hardware
BDM command. A minimum delay of 150 cycles at the clock speed that is active during the data portion of the
command send to change the clock source should occur before the next command can be send. The delay
should be obtained no matter which bit is modied to effectively change the clock source (either PLLSEL bit or
CLKSW bit). This guarantees that the start of the next BDM command uses the new clock for timing subsequent
BDM communications.
Table 15-3 shows the resulting BDM clock source based on the CLKSW and the PLLSEL (PLL select in the CRG
module, the bit is part of the CLKSEL register) bits.
Note: The BDM alternate clock source can only be selected when CLKSW = 0 and PLLSEL = 1. The BDM serial
interface is now fully synchronized to the alternate clock source, when enabled. This eliminates frequency
restriction on the alternate clock which was required on previous versions. Refer to the device
specication to determine which clock connects to the alternate clock source input.
Note: If the acknowledge function is turned on, changing the CLKSW bit will cause the ACK to be at the new
rate for the write command which changes it.
Note: In emulation mode, the CLKSW bit will be set out of RESET.
1
UNSEC
Unsecure — If the device is secured this bit is only writable in special single chip mode from the BDM secure
rmware. It is in a zero state as secure mode is entered so that the secure BDM rmware lookup table is enabled
and put into the memory map overlapping the standard BDM rmware lookup table.
The secure BDM rmware lookup table veries that the on-chip EEPROM and Flash EEPROM are erased. This
being the case, the UNSEC bit is set and the BDM program jumps to the start of the standard BDM rmware
lookup table and the secure BDM rmware lookup table is turned off. If the erase test fails, the UNSEC bit will
not be asserted.
0 System is in a secured mode.
1 System is in a unsecured mode.
Note: When UNSEC is set, security is off and the user can change the state of the secure bits in the on-chip
Flash EEPROM. Note that if the user does not change the state of the bits to “unsecured” mode, the
system will be secured again when it is next taken out of reset.After reset this bit has no meaning or effect
when the security byte in the Flash EEPROM is congured for unsecure mode.
Table 15-2. BDMSTS Field Descriptions (continued)
Field
Description