參數(shù)資料
型號: MC9328MX21CVK
廠商: Freescale Semiconductor
文件頁數(shù): 32/100頁
文件大?。?/td> 0K
描述: IC MCU I.MX21 266MHZ 289-MAPBGA
標準包裝: 152
系列: i.MX21
核心處理器: ARM9
芯體尺寸: 32-位
速度: 266MHz
連通性: 1 線,EBI/EMI,I²C,IrDA,MMC,智能卡,SPI,SSI,UART/USART,USB OTG
外圍設備: DMA,I²S,LCD,POR,PWM,WDT
輸入/輸出數(shù): 192
程序存儲器類型: ROMless
電壓 - 電源 (Vcc/Vdd): 1.45 V ~ 3.3 V
振蕩器型: 外部
工作溫度: -40°C ~ 85°C
封裝/外殼: 289-LFBGA
包裝: 托盤
Specifications
MC9328MX21 Technical Data, Rev. 3.4
Freescale Semiconductor
37
3.12.1
Command Response Timing on MMC/SD Bus
The card identification and card operation conditions timing are processed in open-drain mode. The card
response to the host command starts after exactly NID clock cycles. For the card address assignment,
SET_RCA is also processed in the open-drain mode. The minimum delay between the host command and
card response is NCR clock cycles as illustrated in Figure 26. The symbols for Figure 26 through
Figure 30 are defined in Table 27.
Figure 26. Timing Diagrams at Identification Mode
After a card receives its RCA, it switches to data transfer mode. As shown on the first diagram in
Figure 27, SD_CMD lines in this mode are driven with push-pull drivers. The command is followed by a
period of two Z bits (allowing time for direction switching on the bus) and then by P bits pushed up by the
responding card. The other two diagrams show the separating periods NRC and NCC.
Table 27. State Signal Parameters for Figure 26 through Figure 30
Card Active
Host Active
Symbol
Definition
Symbol
Definition
Z
High impedance state
S
Start bit (0)
D
Data bits
T
Transmitter bit
(Host = 1, Card = 0)
*
Repetition
P
One-cycle pull-up (1)
CRC
Cyclic redundancy check bits (7 bits)
E
End bit (1)
SET_RCA Timing
Identification Timing
Host Command
CID/OCR
NID cycles
CMD
Content
S T
E Z
Z S T
Content
Z Z
******
CRC
Z
Host Command
CID/OCR
NCR cycles
CMD
Content
S T
E Z
Z S T
Content
Z Z
******
CRC
Z
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