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鍙冩暩(sh霉)璩囨枡
| 鍨嬭櫉锛� | MC9328MX21CVK |
| 寤犲晢锛� | Freescale Semiconductor |
| 鏂囦欢闋佹暩(sh霉)锛� | 41/100闋� |
| 鏂囦欢澶�?銆�?/td> | 0K |
| 鎻忚堪锛� | IC MCU I.MX21 266MHZ 289-MAPBGA |
| 妯�(bi膩o)婧�(zh菙n)鍖呰锛� | 152 |
| 绯诲垪锛� | i.MX21 |
| 鏍稿績铏曠悊鍣細 | ARM9 |
| 鑺珨灏哄锛� | 32-浣� |
| 閫熷害锛� | 266MHz |
| 閫ｉ€氭€э細 | 1 绶�锛孍BI/EMI锛孖²C锛孖rDA锛孧MC锛屾櫤鑳藉崱锛孲PI锛孲SI锛孶ART/USART锛孶SB OTG |
| 澶栧湇瑷�(sh猫)鍌欙細 | DMA锛孖²S锛孡CD锛孭OR锛孭WM锛學DT |
| 杓稿叆/杓稿嚭鏁�(sh霉)锛� | 192 |
| 绋嬪簭瀛樺劜鍣ㄩ鍨嬶細 | ROMless |
| 闆诲 - 闆绘簮 (Vcc/Vdd)锛� | 1.45 V ~ 3.3 V |
| 鎸暕鍣ㄥ瀷锛� | 澶栭儴 |
| 宸ヤ綔婧害锛� | -40°C ~ 85°C |
| 灏佽/澶栨锛� | 289-LFBGA |
| 鍖呰锛� | 鎵樼洡 |
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Specifications
MC9328MX21 Technical Data, Rev. 3.4
Freescale Semiconductor
45
Table 29. NFC Target Timing Parameters1,2
1. High is defined as 80% of signal value and low is defined as 20% of signal value. All timings are listed according to this NFC
clock frequency (multiples of NFC clock period) except NF16, which is not NFC clock related.
2. The read data is generated by the NAND Flash device and sampled with the internal NFC clock.
ID
Parameter
Symbol
Relationship to NFC
Clock Period
(T)
NFC Clock
22.17 MHz
T = 45 ns
NFC Clock
33.25 MHz
T = 30 ns
Unit
Min
Max
Min
Max
Min
Max
NF1 NFCLE Setup Time
tCLS
T
鈥�
45
鈥�
30
鈥�
ns
NF2 NFCLE Hold Time
tCLH
T
鈥�
45
鈥�
30
鈥�
ns
NF3 NFCE Setup Time
tCS
T
鈥�
45
鈥�
30
鈥�
ns
NF4 NFCE Hold Time
tCH
T
鈥�
45
鈥�
30
鈥�
ns
NF5 NF_WP Pulse Width
tWP
T
鈥�
45
鈥�
30
鈥�
ns
NF6 NFALE Setup Time
tALS
T
鈥�
45
鈥�
30
鈥�
ns
NF7 NFALE Hold Time
tALH
T
鈥�
45
鈥�
30
鈥�
ns
NF8 Data Setup Time
tDS
T
鈥�
45
鈥�
30
鈥�
ns
NF9 Data Hold Time
tDH
T
鈥�
45
鈥�
30
鈥�
ns
NF10 Write Cycle Time
tWC
2T
鈥�
90
鈥�
60
鈥�
ns
NF11 NFWE Hold Time
tWH
T
鈥�
45
鈥�
30
鈥�
ns
NF12 Ready to NFRE Low
tRR
4T
鈥�
180
鈥�
120
鈥�
ns
NF13 NFRE Pulse Width
tRP
1.5T
鈥�
67.5
鈥�
45
鈥�
ns
NF14 READ Cycle Time
tRC
2T
鈥�
90
鈥�
60
鈥�
ns
NF15 NFRE High Hold Time
tREH
0.5T
鈥�
22.5
鈥�
15
鈥�
ns
NF16 Data Setup on READ
tDSR
15
鈥�
15
鈥�
15
鈥�
ns
NF17 Data Hold on READ
tDHR
0
鈥�
0
鈥�
0
鈥�
ns
鐩搁棞(gu膩n)PDF璩囨枡 |
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鐩搁棞(gu膩n)浠ｇ悊鍟�/鎶€琛�(sh霉)鍙冩暩(sh霉) |
鍙冩暩(sh霉)鎻忚堪 |
|---|---|
| MC9328MX21CVK | 鍒堕€犲晢:Freescale Semiconductor 鍔熻兘鎻忚堪:Microcontroller |
| MC9328MX21CVKR2 | 鍔熻兘鎻忚堪:铏曠悊鍣� - 灏堥杸鎳�(y墨ng)鐢� DB I.MX21 PB-FR RoHS:鍚� 鍒堕€犲晢:Freescale Semiconductor 椤炲瀷:Multimedia Applications 鏍稿績:ARM Cortex A9 铏曠悊鍣ㄧ郴鍒�:i.MX6 鏁�(sh霉)鎿�(j霉)绺界窔瀵害:32 bit 鏈€澶ф檪(sh铆)閻橀牷鐜�:1 GHz 鎸囦护/鏁�(sh霉)鎿�(j霉)绶╁瓨: 鏁�(sh霉)鎿�(j霉) RAM 澶у皬:128 KB 鏁�(sh霉)鎿�(j霉) ROM 澶у皬: 宸ヤ綔闆绘簮闆诲: 鏈€澶у伐浣滄韩搴�:+ 95 C 瀹夎棰�(f膿ng)鏍�:SMD/SMT 灏佽 / 绠遍珨:MAPBGA-432 |
| MC9328MX21CVM | 鍔熻兘鎻忚堪:铏曠悊鍣� - 灏堥杸鎳�(y墨ng)鐢� DB I.MX21 17X17 PB-FR RoHS:鍚� 鍒堕€犲晢:Freescale Semiconductor 椤炲瀷:Multimedia Applications 鏍稿績:ARM Cortex A9 铏曠悊鍣ㄧ郴鍒�:i.MX6 鏁�(sh霉)鎿�(j霉)绺界窔瀵害:32 bit 鏈€澶ф檪(sh铆)閻橀牷鐜�:1 GHz 鎸囦护/鏁�(sh霉)鎿�(j霉)绶╁瓨: 鏁�(sh霉)鎿�(j霉) RAM 澶у皬:128 KB 鏁�(sh霉)鎿�(j霉) ROM 澶у皬: 宸ヤ綔闆绘簮闆诲: 鏈€澶у伐浣滄韩搴�:+ 95 C 瀹夎棰�(f膿ng)鏍�:SMD/SMT 灏佽 / 绠遍珨:MAPBGA-432 |
| MC9328MX21CVM | 鍒堕€犲晢:Freescale Semiconductor 鍔熻兘鎻忚堪:Microprocessor |
| MC9328MX21CVMR2 | 鍔熻兘鎻忚堪:铏曠悊鍣� - 灏堥杸鎳�(y墨ng)鐢� DB I.MX21 17X17 PB-FR RoHS:鍚� 鍒堕€犲晢:Freescale Semiconductor 椤炲瀷:Multimedia Applications 鏍稿績:ARM Cortex A9 铏曠悊鍣ㄧ郴鍒�:i.MX6 鏁�(sh霉)鎿�(j霉)绺界窔瀵害:32 bit 鏈€澶ф檪(sh铆)閻橀牷鐜�:1 GHz 鎸囦护/鏁�(sh霉)鎿�(j霉)绶╁瓨: 鏁�(sh霉)鎿�(j霉) RAM 澶у皬:128 KB 鏁�(sh霉)鎿�(j霉) ROM 澶у皬: 宸ヤ綔闆绘簮闆诲: 鏈€澶у伐浣滄韩搴�:+ 95 C 瀹夎棰�(f膿ng)鏍�:SMD/SMT 灏佽 / 绠遍珨:MAPBGA-432 |
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