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參數(shù)資料
| 型號： | MC9328MX21CVMR2 |
| 廠商： | Freescale Semiconductor |
| 文件頁數(shù)： | 6/100頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC MCU I.MX21 266MHZ 289-MAPBGA |
| 標準包裝： | 1,000 |
| 系列： | i.MX21 |
| 核心處理器： | ARM9 |
| 芯體尺寸： | 32-位 |
| 速度： | 266MHz |
| 連通性： | 1 線，EBI/EMI，I²C，IrDA，MMC，智能卡，SPI，SSI，UART/USART，USB OTG |
| 外圍設備： | DMA，I²S，LCD，POR，PWM，WDT |
| 輸入/輸出數(shù)： | 192 |
| 程序存儲器類型： | ROMless |
| 電壓 - 電源 (Vcc/Vdd)： | 1.45 V ~ 3.3 V |
| 振蕩器型： | 外部 |
| 工作溫度： | -40°C ~ 85°C |
| 封裝/外殼： | 289-LFBGA |
| 包裝： | 帶卷 (TR) |
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Signal Descriptions
MC9328MX21 Technical Data, Rev. 3.4
Freescale Semiconductor
13
SYS_CLK1
SSI1 master clock. Multiplexed with TOUT.
SSI2_CLK
Serial clock signal which is output in master or input in slave.
SSI2_TXD
Transmit serial data signal
SSI2_RXD
Receive serial data
SSI2_FS
Frame Sync signal which is output in master and input in slave.
SYS_CLK2
SSI2 master clock. Multiplexed with TOUT.
SSI3_CLK
Serial clock signal which is output in master or input in slave. Multiplexed with SLCDC2_CLK
SSI3_TXD
Transmit serial data signal which is multiplexed with SLCDC2_CS
SSI3_RXD
Receive serial data which is multiplexed with SLCDC2_RS
SSI3_FS
Frame Sync signal which is output in master and input in slave. Multiplexed with SLCDC2_D0.
SAP_CLK
Serial clock signal which is output in master or input in slave.
SAP_TXD
Transmit serial data
SAP_RXD
Receive serial data
SAP_FS
Frame Sync signal which is output in master and input in slave.
I2C
I2C_CLK
I2C Clock
I2C_DATA
I2C Data
1-Wire
OWIRE
1-Wire input and output signal. This signal is multiplexed with JTAG RTCK.
PWM
PWMO
PWM Output. This signal is multiplexed with PC_SPKOUT of PCMCIA, as well as TOUT2 and TOUT3
of the General Purpose Timer module.
General Purpose Input/Output
PF[16]
Dedicated GPIO. When unused, program this signal as an input with the on-chip pull-up resistor
enabled.
Keypad
KP_COL[7:0]
Keypad Column selection signals. KP_COL[7:6] are multiplexed with UART2_CTS and UART2_TXD
respectively. Alternatively, KP_COL6 is also available on the internal factory test signal TEST_WB2. The
Function Multiplexing Control Register in the System Control chapter must be used in conjunction with
programming the GPIO multiplexing (to select the alternate signal multiplexing) to choose which signal
KP_COL6 is available.
KP_ROW[7:0]
Keypad Row selection signals. KP_ROW[7:6] are multiplexed with UART2_RTS and UART2_RXD
signals respectively. Alternatively, KP_ROW7 and KP_ROW6 are available on the internal factory test
signals TEST_WB0 and TEST_WB1 respectively. The Function Multiplexing Control Register in the
System Control chapter must be used in conjunction with programming the GPIO multiplexing (to select
the alternate signal multiplexing) to choose which signals KP_ROW6 and KP_ROW7 are available.
Noisy Supply Pins
NVDD
Noisy Supply for the I/O pins. There are six (6) I/O voltages, NVDD1 through NVDD6.
NVSS
Noisy Ground for the I/O pins
Table 2. i.MX21 Signal Descriptions (Continued)
Signal Name
Function/Notes
相關PDF資料 |
PDF描述 |
|---|---|
| VI-BN3-IY-F3 | CONVERTER MOD DC/DC 24V 50W |
| VI-BN2-IY-F2 | CONVERTER MOD DC/DC 15V 50W |
| MC9328MX21CVM | IC MCU I.MX21 266MHZ 289-MAPBGA |
| MC9328MX21VKR2 | IC MCU I.MX21 266MHZ 289-MAPBGA |
| MC9328MX21DVKR2 | IC MCU I.MX21 266MHZ 289-MAPBGA |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| MC9328MX21DVG | 制造商:Rochester Electronics LLC 功能描述:DB I.MX21 - Bulk 制造商:Motorola Inc 功能描述: 制造商:MOTOROLA 功能描述: |
| MC9328MX21DVGR2 | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| MC9328MX21DVH | 制造商:MOTOROLA 制造商全稱:Motorola, Inc 功能描述:i.MX family of microprocessors |
| MC9328MX21DVK | 功能描述:處理器 - 專門應用 DB I.MX21 PB-FR RoHS:否 制造商:Freescale Semiconductor 類型:Multimedia Applications 核心:ARM Cortex A9 處理器系列:i.MX6 數(shù)據(jù)總線寬度:32 bit 最大時鐘頻率:1 GHz 指令/數(shù)據(jù)緩存: 數(shù)據(jù) RAM 大小:128 KB 數(shù)據(jù) ROM 大小: 工作電源電壓: 最大工作溫度:+ 95 C 安裝風格:SMD/SMT 封裝 / 箱體:MAPBGA-432 |
| MC9328MX21DVK | 制造商:Freescale Semiconductor 功能描述:Microprocessor |
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