參數(shù)資料
型號(hào): MC9328MX21VMR2
廠商: Freescale Semiconductor
文件頁數(shù): 68/100頁
文件大小: 0K
描述: IC MCU I.MX21 266MHZ 289-MAPBGA
標(biāo)準(zhǔn)包裝: 1,000
系列: i.MX21
核心處理器: ARM9
芯體尺寸: 32-位
速度: 266MHz
連通性: 1 線,EBI/EMI,I²C,IrDA,MMC,智能卡,SPI,SSI,UART/USART,USB OTG
外圍設(shè)備: DMA,I²S,LCD,POR,PWM,WDT
輸入/輸出數(shù): 192
程序存儲(chǔ)器類型: ROMless
電壓 - 電源 (Vcc/Vdd): 1.45 V ~ 3.3 V
振蕩器型: 外部
工作溫度: 0°C ~ 70°C
封裝/外殼: 289-LFBGA
包裝: 帶卷 (TR)
Signal Descriptions
MC9328MX21 Technical Data, Rev. 3.4
Freescale Semiconductor
7
Clocks and Resets
EXTAL26M
Crystal input (26MHz), or a 16 MHz to 32 MHz oscillator (or square-wave) input when the internal
oscillator circuit is shut down. When using an external signal source, feed this input with a square wave
signal switching from GND to VDDA.
XTAL26M
Oscillator output to external crystal. When using an external signal source, float this output.
EXTAL32K
32 kHz or 32.768 kHz crystal input. When using an external signal source, feed this input with a square
wave signal switching from GND to QVDD5.
XTAL32K
Oscillator output to external crystal. When using an external signal source, float this output.
CLKO
Clock Out signal selected from internal clock signals. Please refer to clock controller for internal clock
selection.
EXT_48M
This is a special factory test signal. To ensure proper operation, connect this signal to ground.
EXT_266M
This is a special factory test signal. To ensure proper operation, connect this signal to ground.
RESET_IN
Master Reset—External active low Schmitt trigger input signal. When this signal goes active, all modules
(except the reset module, SDRAMC module, and the clock control module) are reset.
RESET_OUT
Reset Out—Internal active low output signal from the Watchdog Timer module and is asserted from the
following sources: Power-on reset, External reset (RESET_IN), and Watchdog time-out.
POR
Power On Reset—Active low Schmitt trigger input signal. The POR signal is normally generated by an
external RC circuit designed to detect a power-up event.
CLKMODE[1:0]
These are special factory test signals. To ensure proper operation, leave these signals as no connects.
OSC26M_TEST
This is a special factory test signal. To ensure proper operation, leave this signal as a no connect.
TEST_WB[2:0]
These are special factory test signals. However, these signals are also multiplexed with GPIO PORT E
as well as alternate keypad signals. If not using these signals for GPIO functions or for other multiplexed
functions, then configure as GPIO input with pull-up enabled, and leave as a no connect.
TEST_WB[4:3]
These are special factory test signals. To ensure proper operation, leave these signals as no connects.
WKGD
Battery indicator input used to qualify the walk-up process. Also multiplexed with TIN.
JTAG
For termination recommendations, see the Table “JTAG pinouts” in the Multi-ICE User Guide from ARM Limited.
TRST
Test Reset Pin—External active low signal used to asynchronously initialize the JTAG controller.
TDO
Serial Output for test instructions and data. Changes on the falling edge of TCK.
TDI
Serial Input for test instructions and data. Sampled on the rising edge of TCK.
TCK
Test Clock to synchronize test logic and control register access through the JTAG port.
TMS
Test Mode Select to sequence the JTAG test controller’s state machine. Sampled on the rising edge of
TCK.
JTAG_CTRL
JTAG Controller select signal—JTAG_CTRL is sampled during the rising edge of TRST. Must be pulled
to logic high for proper JTAG interface to debugger. Pulling JTAG_CRTL low is for internal test purposes
only.
RTCK
JTAG Return Clock used to enhance stability of JTAG debug interface devices. This signal is multiplexed
with 1-Wire, therefore using 1-Wire renders RTCK unusable and vice versa.
CMOS Sensor Interface
CSI_D [7:0]
Sensor port data
CSI_MCLK
Sensor port master clock
Table 2. i.MX21 Signal Descriptions (Continued)
Signal Name
Function/Notes
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