參數(shù)資料
型號(hào): MC9328MXSVF10
廠商: FREESCALE SEMICONDUCTOR INC
元件分類: 微控制器/微處理器
英文描述: 32-BIT, 100 MHz, MICROPROCESSOR, PBGA225
封裝: 13 X 13 MM, PLASTIC, BGA-225
文件頁數(shù): 60/72頁
文件大?。?/td> 1411K
代理商: MC9328MXSVF10
Specifications
MC9328MXS Advance Information, Rev. 0
Freescale Semiconductor
63
3.15 I2C Module
The I2C communication protocol consists of seven elements: START, Data Source/Recipient, Data Direction,
Slave Acknowledge, Data, Data Acknowledge, and STOP.
Figure 52. Definition of Bus Timing for I2C
3.16 Synchronous Serial Interface
The transmit and receive sections of the SSI can be synchronous or asynchronous. In synchronous mode, the
transmitter and the receiver use a common clock and frame synchronization signal. In asynchronous mode, the
transmitter and receiver each have their own clock and frame synchronization signals. Continuous or gated clock
mode can be selected. In continuous mode, the clock runs continuously. In gated clock mode, the clock functions
only during transmission. The internal and external clock timing diagrams are shown in Figure 54 through
Normal or network mode can also be selected. In normal mode, the SSI functions with one data word of
I/O per frame. In network mode, a frame can contain between 2 and 32 data words. Network mode is typically used
in star or ring-time division multiplex networks with other processors or codecs, allowing interface to time division
multiplexed networks without additional logic. Use of the gated clock is not allowed in network mode. These
distinctions result in the basic operating modes that allow the SSI to communicate with a wide variety of devices.
Table 31. I2C Bus Timing Parameter Table
Ref No.
Parameter
1.8 ± 0.1 V
3.0 ± 0.3 V
Unit
Minimum
Maximum
Minimum
Maximum
1
Hold time (repeated) START condition
182
160
ns
2
Data hold time
01710150
ns
3
Data setup time
11.4
10
ns
4
HIGH period of the SCL clock
80
120
ns
5
LOW period of the SCL clock
480
320
ns
6
Setup time for STOP condition
182.4
160
ns
SDA
SCL
1
2
3
4
6
5
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