參數(shù)資料
型號: MC9RS08KA2CSCR
廠商: Freescale Semiconductor
文件頁數(shù): 113/136頁
文件大?。?/td> 0K
描述: IC MCU 8BIT 2K FLASH 8-SOIC
產(chǎn)品培訓模塊: Mechatronics
USBSpyder08 Discovery Kit
RS08KA2 Low-End Microcontroller Series
MC9RS08KA8 Microcontroller
標準包裝: 1
系列: RS08
核心處理器: RS08
芯體尺寸: 8-位
速度: 10MHz
外圍設備: LVD,POR,WDT
輸入/輸出數(shù): 4
程序存儲器容量: 2KB(2K x 8)
程序存儲器類型: 閃存
RAM 容量: 63 x 8
電壓 - 電源 (Vcc/Vdd): 1.8 V ~ 5.5 V
振蕩器型: 內部
工作溫度: -40°C ~ 85°C
封裝/外殼: 8-SOIC(0.154",3.90mm 寬)
包裝: 標準包裝
其它名稱: MC9RS08KA2CSCRDKR
Internal Clock Source (RS08ICSV1)
MC9RS08KA2 Series Data Sheet, Rev. 4
78
Freescale Semiconductor
9.3.2
ICS Control Register 2 (ICSC2)
7
6
5
432
1
0
R0
CLKS
00
0
00
IREFSTEN
W
Reset:
0
= Unimplemented
Figure 9-3. ICS Control Register 1 (ICSC1)
Table 9-2. ICSC1 Field Descriptions
Field
Description
6
CLKS
Clock Source Select — Selects the clock source that controls the bus frequency. The actual bus frequency
depends on the value of the BDIV bits.
0 Output of FLL is selected
1 Internal reference clock is selected
0
IREFSTEN
Internal Reference Stop Enable — Controls whether the internal reference clock remains enabled when the
ICS enters stop mode.
1 Internal reference clock remains enabled in stop
0 Internal reference clock is disabled in stop
7
6
5
432
1
0
R
BDIV
00
LP
00
0
W
Reset:
0
1
0
000
0
= Unimplemented
Figure 9-4. ICS Control Register 2 (ICSC2)
Table 9-3. ICSC2 Field Descriptions
Field
Description
7:6
BDIV
Bus Frequency Divider — Selects the amount to divide down the clock source selected by the CLKS bit. This
controls the bus frequency.
00 Encoding 0 — Divides selected clock by 1
01 Encoding 1 — Divides selected clock by 2 (reset default)
10 Encoding 2 — Divides selected clock by 4
11 Encoding 3 — Divides selected clock by 8
3
LP
Low Power Select — Controls whether the FLL is disabled in FLL bypassed modes.
1
FLL is disabled in bypass modes
0
FLL is not disabled in bypass mode
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