參數(shù)資料
型號： MC9RS08KA2CSCR
廠商： Freescale Semiconductor
文件頁數(shù)： 8/136頁
文件大?。?/td> 0K
描述： IC MCU 8BIT 2K FLASH 8-SOIC
產(chǎn)品培訓模塊： Mechatronics
USBSpyder08 Discovery Kit
RS08KA2 Low-End Microcontroller Series
MC9RS08KA8 Microcontroller
標準包裝： 1
系列： RS08
核心處理器： RS08
芯體尺寸： 8-位
速度： 10MHz
外圍設(shè)備： LVD，POR，WDT
輸入/輸出數(shù)： 4
程序存儲器容量： 2KB（2K x 8）
程序存儲器類型： 閃存
RAM 容量： 63 x 8
電壓 - 電源 (Vcc/Vdd)： 1.8 V ~ 5.5 V
振蕩器型： 內(nèi)部
工作溫度： -40°C ~ 85°C
封裝/外殼： 8-SOIC（0.154"，3.90mm 寬）
包裝： 標準包裝
其它名稱： MC9RS08KA2CSCRDKR
Chapter 12 Development Support
MC9RS08KA2 Series Data Sheet, Rev. 4
Freescale Semiconductor
105
12.5
RS08 BDC Commands
BDC commands are sent serially from a host computer to the BKGD pin of the target MCU. All commands
and data are sent MSB-first using a custom BDC communications protocol. Active background mode
commands require that the target MCU is currently in the active background mode while non-intrusive
commands may be issued at any time whether the target MCU is in active background mode or running a
user application program.
Table 12-2 shows all RS08 BDC commands, a shorthand description of their coding structure, and the
meaning of each command.
Coding Structure Nomenclature
The following nomenclature is used in Table 12-2 to describe the coding structure of the BDC commands.
Commands begin with an 8-bit command code in the host-to-target direction
(most significant bit first)
/
=
Separates parts of the command
d
=
Delay 16 to 511 target BDC clock cycles
soft-reset
=
Delay of at least 512 BDC clock cycles from last host falling-edge
AAAA
=
16-bit address in the host-to-target direction1
RD
=
Eight bits of read data in the target-to-host direction
WD
=
Eight bits of write data in the host-to-target direction
RD16
=
16 bits of read data in the target-to-host direction
WD16
=
16 bits of write data in the host-to-target direction
SS
=
the contents of BDCSCR in the target-to-host direction (STATUS)
CC
=
Eight bits of write data for BDCSCR in the host-to-target direction (CONTROL)
RBKP
=
16 bits of read data in the target-to-host direction (from BDCBKPT breakpoint
register)
WBKP
=
16 bits of write data in the host-to-target direction (for BDCBKPT breakpoint
register)
15
14
13
12
11
10
9
8765
4321
0
R0
0
A13
A12
A11
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
W
Any
Reset
0
0000
000
0000
= Unimplemented or Reserved
Figure 12-7. BDC Breakpoint Match Register (BDCBKPT)
1. The RS08 CPU uses only 14 bits of address and occupies the lower 14 bits of the 16-bit AAAA address field. The values of
address bits 15 and 14 in AAAA are truncated and thus do not matter.
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