Chapter 7 Central Processor Unit (S08CPUV3)
MC9S08DV60 Series Data Sheet, Rev 3
130
Freescale Semiconductor
TXS
Transfer Index Reg. to SP
SP
← (H:X) – $0001
INH
94
2
fp
–11– ––––
WAIT
Enable Interrupts; Wait for Interrupt
I bit
← 0; Halt CPU
INH
8F
2+
fp...
–11– 0–––
Source Form: Everything in the source forms columns, except expressions in italic characters, is literal information which must appear in the
assembly source le exactly as shown. The initial 3- to 5-letter mnemonic and the characters (#, ( ) and +) are always a literal characters.
n
Any label or expression that evaluates to a single integer in the range 0-7.
opr8i
Any label or expression that evaluates to an 8-bit immediate value.
opr16i
Any label or expression that evaluates to a 16-bit immediate value.
opr8a
Any label or expression that evaluates to an 8-bit direct-page address ($00xx).
opr16a
Any label or expression that evaluates to a 16-bit address.
oprx8
Any label or expression that evaluates to an unsigned 8-bit value, used for indexed addressing.
oprx16
Any label or expression that evaluates to a 16-bit value, used for indexed addressing.
rel
Any label or expression that refers to an address that is within –128 to +127 locations from the start of the next instruction.
Operation Symbols:
A
Accumulator
CCR
Condition code register
H
Index register high byte
M
Memory location
n
Any bit
opr
Operand (one or two bytes)
PC
Program counter
PCH
Program counter high byte
PCL
Program counter low byte
rel
Relative program counter offset byte
SP
Stack pointer
SPL
Stack pointer low byte
X
Index register low byte
&
Logical AND
|
Logical OR
⊕
Logical EXCLUSIVE OR
( )
Contents of
+
Add
–
Subtract, Negation (two’s complement)
×
Multiply
÷
Divide
#
Immediate value
←
Loaded with
:
Concatenated with
Addressing Modes:
DIR
Direct addressing mode
EXT
Extended addressing mode
IMM
Immediate addressing mode
INH
Inherent addressing mode
IX
Indexed, no offset addressing mode
IX1
Indexed, 8-bit offset addressing mode
IX2
Indexed, 16-bit offset addressing mode
IX+
Indexed, no offset, post increment addressing mode
IX1+
Indexed, 8-bit offset, post increment addressing mode
REL
Relative addressing mode
SP1
Stack pointer, 8-bit offset addressing mode
SP2
Stack pointer 16-bit offset addressing mode
Cycle-by-Cycle Codes:
f
Free cycle. This indicates a cycle where the CPU
does not require use of the system buses. An f
cycle is always one cycle of the system bus clock
and is always a read cycle.
p
Program fetch; read from next consecutive
location in program memory
r
Read 8-bit operand
s
Push (write) one byte onto stack
u
Pop (read) one byte from stack
v
Read vector from $FFxx (high byte rst)
w
Write 8-bit operand
CCR Bits:
V
Overow bit
H
Half-carry bit
I
Interrupt mask
N
Negative bit
Z
Zero bit
C
Carry/borrow bit
CCR Effects:
Set or cleared
–
Not affected
U
Undened
Table 7-2. Instruction Set Summary (Sheet 9 of 9)
Source
Form
Operation
Ad
dress
Mode
Object Code
Cyc
les
Cyc-by-Cyc
Details
Affect
on CCR
V 1 1 H I N Z C