參數(shù)資料
型號: MC9S08MM128VLH
廠商: FREESCALE SEMICONDUCTOR INC
元件分類: 微控制器/微處理器
英文描述: 8-BIT, FLASH, 48 MHz, MICROCONTROLLER, PQFP64
封裝: 10 X 10 MM, 1.60 MM HEIGHT, ROHS COMPLIANT, LQFP-64
文件頁數(shù): 18/50頁
文件大小: 970K
代理商: MC9S08MM128VLH
Preliminary Electrical Characteristics
Freescale Semiconductor
25
Figure 6. Offset at Half Scale vs Temperature
Table 14. DAC 12-Bit Operating Behaviors
#
Characteristic
Symbol
Min
Max
Unit
C
Notes
1
Resolution
N
12
bit
C
2
Supply current low-power mode
IDDA_DACLP
50
100
A
C
3
Supply current high-power mode
IDDA_DACHP
120
500
(TBD)
A
C
4
Full-scale Settling time
(±0.5 LSB)
(0x080 to 0xF7F or 0xF7F to 0x080)
low-power mode
TsFSLP
200
(TBD)
s
C
5
Full-scale Settling time
(±0.5 LSB)
(0x080 to 0xF7F or 0xF7F to 0x080)
high-power mode
TsFSHP
—30
s
C
6
Code-to-code Settling time
(±0.5 LSB)
(0xBF8 to 0xC08 or 0xC08 to
0xBF8)
low-power mode
TsC-CLP
—5
s
C
7
Code-to-code Settling time
(±0.5 LSB)
(0xBF8 to 0xC08 or 0xC08 to
0xBF8)
high-power mode
TsC-CHP
—1(TBD)
s
C
8
DAC output voltage range low
(high-power mode, no load, DAC
set to 0)
Vdacoutl
100
(TBD)
mV
C
9
DAC output voltage range high
(high-power mode, no load, DAC
set to 0x0FFF)
Vdacouth
VDACR-
100
—mV
C
10
Integral non-linearity error
INL
—± 8
LSB
C
11
Differential non-linearity error
VDACR is > 2.4 V
DNL
—± 1
LSB
C
12
Offset error
EO
—± 0.5
%FSR
C
13
Gain error
EG
± 0.5
(TBD)
%FSR
C
14
Power supply rejection ratio
VDD ≥ 2.4 V
PSRR
60
dB
C
15
Temperature drift of offset voltage
(DAC set to 0x0800)
Tco
2
(TBD)
mV
C
See Typical
Drift figure that
follows.
16
Offset aging coefficient
Ac
TBD
V/yr
C
Non-Disclosure Agreement Required
Preliminary — Subject to Change
Because
of
an
order
from
the
United
States
International
Trade
Commission,
BGA-packaged
product
lines
and
part
numbers
indicated
here
currently
are
not
available
from
Freescale
for
import
or
sale
in
the
United
States
prior
to
September
2010:
MC9S08MM128
products
in
81
MAPBGA
packages
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