Serial Communications Interface (S08SCIV1)
MC9S08RC/RD/RE/RG Data Sheet, Rev. 1.11
158
Freescale Semiconductor
the transmit data register is transferred to the shift register (synchronized with the baud rate clock) and the
transmit data register empty (TDRE) status ag is set to indicate another character may be written to the
transmit data buffer at SCI1D.
If no new character is waiting in the transmit data buffer after a stop bit is shifted out the TxD1 pin, the
transmitter sets the transmit complete ag and enters an idle mode, with TxD1 high, waiting for more
characters to transmit.
Writing 0 to TE does not immediately release the pin to be a general-purpose I/O pin. Any transmit activity
that is in progress must rst be completed. This includes data characters in progress, queued idle
characters, and queued break characters.
12.3.2.1
Send Break and Queued Idle
The SBK control bit in SCI1C2 is used to send break characters which were originally used to gain the
attention of old teletype receivers. Break characters are a full character time of logic 0 (10 bit times
including the start and stop bits). Normally, a program would wait for TDRE to become set to indicate the
last character of a message has moved to the transmit shifter, then write 1 and then write 0 to the SBK bit.
This action queues a break character to be sent as soon as the shifter is available. If SBK is still 1 when the
queued break moves into the shifter (synchronized to the baud rate clock), an additional break character is
queued. If the receiving device is another Freescale Semiconductor SCI, the break characters will be
received as 0s in all eight data bits and a framing error (FE = 1) occurs.
When idle-line wakeup is used, a full character time of idle (logic 1) is needed between messages to wake
up any sleeping receivers. Normally, a program would wait for TDRE to become set to indicate the last
character of a message has moved to the transmit shifter, then write 0 and then write 1 to the TE bit. This
action queues an idle character to be sent as soon as the shifter is available. As long as the character in the
shifter does not nish while TE = 0, the SCI transmitter never actually releases control of the TxD1 pin. If
there is a possibility of the shifter nishing while TE = 0, set the general-purpose I/O controls so the pin
that is shared with TxD1 is an output driving a logic 1. This ensures that the TxD1 line will look like a
normal idle line even if the SCI loses control of the port pin between writing 0 and then 1 to TE.
12.3.3
Receiver Functional Description
In this section, the data sampling technique used to reconstruct receiver data is described in more detail;
two variations of the receiver wakeup function are explained. (The receiver block diagram is shown in
The receiver is enabled by setting the RE bit in SCI1C2. Character frames consist of a start bit of logic 0,
eight (or nine) data bits (LSB rst), and a stop bit of logic 1. For information about 9-bit data mode, refer
is congured for normal 8-bit data mode.
After receiving the stop bit into the receive shifter, and provided the receive data register is not already full,
the data character is transferred to the receive data register and the receive data register full (RDRF) status
ag is set. If RDRF was already set indicating the receive data register (buffer) was already full, the overrun
(OR) status ag is set and the new data is lost. Because the SCI receiver is double-buffered, the program