參數(shù)資料
型號： MCAQE32G8APP-0XA
元件分類： 存儲控制器/管理單元
英文描述： FLASH MEMORY DRIVE CONTROLLER, PQFP
封裝： LQFP
文件頁數(shù)： 10/62頁
文件大小： 740K
代理商： MCAQE32G8APP-0XA
NAND Flash-based Solid State Disk
18
Nov. 15. 2006
Figure 3 through Figure 6 define the timing associated with Multiword DMA transfers.
For Multiword DMA modes 1 and above, the minimum value of t0 is specified by word 65 in the IDENTIFY DEVICE parameter list.
Table 3 defines the minimum value that shall be placed in word 65.
Devices shall power-up with mode 0 as the default Multiword DMA mode.
Table 3 - Multiword DMA data transfer
NOTE:
> t0 is the minimum total cycle time, tD is the minimum DIOR-/DIOW- assertion time, and tK (tKR or tKw, as appropriate) is the minimum DIOR-/DIOW-
negation time. A host shall lengthen tD and/or tK to ensure that t0 is equal to the value reported in the devices IDENTIFY DEVICE data.
Multiword DMA timing parameters
Mode 0ns
Mode 1ns
Mode 2ns
Note
t0
Cycle time
min
480
150
120
see note
tD
DIOR-/DIOW- asserted pulse width
min
215
80
70
see note
tE
DIOR- data access
max
150
60
50
tF
DIOR- data hold
min
5
tG
DIOR-/DIOW-data setup
min
100
30
20
tH
DIOW- data hold
min
20
15
10
tI
DMACK to DIOR-/DIOW- data setup
min
0
tJ
DIOR-/DIOW- to DMACK hold
min
20
5
tKR
DIOR- negated pulse width
min
50
25
see note
tKW
DIOW- negated pulse width
min
215
50
25
see note
tLR
DIOR- to DMARQ delay
max
120
40
35
tLW
DIOW- to DMARQ delay
max
40
35
tM
CS(1:0) valid to DIOR-/DIOW-
min
50
30
25
tN
CS(1:0) hold
min
15
10
tZ
DMACK- to read data released
max
20
25
4.6.3 Multiword DMA Data Transfers
相關(guān)PDF資料
PDF描述
MC908AZ32AVFU 8-BIT, FLASH, 8.4 MHz, MICROCONTROLLER, PQFP64
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